Date/Time
Date(s) - 03/17/2021
12:00 - 13:00
Add to Google Calendar or iCal/Outlook Calendar


Dr. Avesta Sasan, George Mason University

Abstract:

Today, Integrated Circuit (IC) supply chain is globally distributed. The involvement of untrusted or less trusted entities in the IC supply chain has raised many concerns over the safety and security of the manufactured ICs. Besides, since the intellectual property embedded in a netlist is available in its raw and unencrypted form to many entities in the chain, spacially in the fabrication stage, many have raised concerns over the possible piracy or theft of intellectual property. To protect the IP in the manufacturing supply chain, researchers in the domain of hardware security have proposed the concept of Logic Encryption. In an encrypted netlist, the design house introduces a mean of post-manufacturing programmability of hardened logic function into the netlist, making the netlist’s function dependent on a key-value. After the IC is fabricated, it is shipped to a trusted activation house, where it is activated after storing the key in a tamper-proof nonvolatile memory. The logic encryption, however, has to resist adversarial attacks. Since 2008, when the idea of logic encryption was proposed, many logic encryption techniques have been proposed. However, shortly after publication, many of these solutions were broken by a new attack. In this Webinar, we will review many of these attacks and discuss the state of the art attacks that logic encryption solutions have to resist. The goal of this Webinar is to raise awareness about the capabilities of adversaries and existing solutions for attacking and decrypting logic encryption solutions.

Intended Learning Outcomes (ILOs)

Upon the completion of this webinar, trainees should be able to:

  • Understand the motivation and the goal of logic encryption
  • Become familiar with the state of the art attacks against logic encryption solutions
  • Understand the scope and assumption for the state of the art attack solutions, and become aware of when these attacks are applicable.

Target Audience:

IC designers that are interested in the protection of intellectual property, graduate students in the domain of hardware security, researchers interested in entering the field of hardware security.

Short Biography:

Avesta Sasan received his BS in computer engineering from the University of California Irvine in 2005. He then received his MS and PhD in electrical and computer engineering from the University of California Irvine in 2006 and 2010 respectively. In 2010, Sasan joined the office of the chief technology officer at Broadcom Co. He worked on the physical design and implementation of ARM processors, serving as a physical designer, timing sign off specialist, and the lead of signal and power integrity sign off in this team. In 2014, Sasan was recruited by Qualcomm’s office of VLSI technology. In this role, Sasan developed different methodologies and in-house EDA’s for accurate sign-off and analysis of hardened ASIC solutions. Sasan joined George Mason University in 2016, and he is currently serving as an Associate Professor in the Department of Electrical and Computer Engineering. Sasan’s research spans low power design methodology, hardware security, computer security, cybersecurity, accelerated computing, approximate computing, machine learning, and neuromorphic computing.

 

Registration