1:00pm to 4:00pm EST
Thursday, June 11th, 2020
This training will be conducted online through Zoom due to COVID-19
Presenter: Dr. Eslam Tawfik, Ohio State University
Who can attend: For Government and DIB Employees Only
To register email: Amanda Moscrip at firstname.lastname@example.org, include name, affiliation, and name of the organization.
Deadline: Register ASAP – Seating is limited.
Digital design flow is a lengthy process that involves many steps to take the design from RTL to the final phase. The objective of this training is to demystify this field and provide in-depth understanding of the transformations in each design step.
Specifically, this training will focus on fundamental elements in the design process such as, event‑driven simulation, synthesis, timing analysis, technology files, standard cell views, physical design, and signoff checks. Throughout the training, attendees will learn the salient differences in these elements when using FPGA and ASIC platforms.
Intended Learning Outcomes (ILOs)
Upon the completion of this training, trainees should be able to:
- Holistically understand digital design flow (from the specification phase to the signoff checks).
- Learn all transformations that occur during the design flow.
- Gain knowledge on the different technology files and standard cell views.
- Identify different design flows based on the target implementation technology (ASIC vs. FPGA).
- Understand timing-analysis and timing-closure.
- Understand chip level planning.
Product and verification engineers as well as system and computer architecture engineers and decision-makers who are interested in understanding digital IC design flow; entry-level design engineers who want to grasp the full digital design cycle; senior undergraduate and post-graduate students (who are preparing to get involved in digital IC design, research and development).