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UID:93@mestcenter.org
DTSTART;TZID=America/New_York:20220406T120000
DTEND;TZID=America/New_York:20220406T130000
DTSTAMP:20240905T133327Z
URL:https://mestcenter.org/training/fault-criticality-assessment-in-ai-acc
elerators/
SUMMARY:Webinar: Fault Criticality Assessment in AI Accelerators
DESCRIPTION:To watch the recorded webinar\, click on the recording.\nPlay V
ideo\nSpeaker: \nDr. Krishnendu Chakrabarty\, John Cocke Distinguished Pr
ofessor\, Chair of Department of Electrical and Computer Engineering Profe
ssor of Computer Science Duke University\nAbstract:\nThe ubiquitous applic
ation of deep neural networks (DNN) has led to a rise in demand for AI acc
elerators. For example\, the Tensor Processing Unit from Google and its va
riants are of considerable interest for DNN inferencing using AI accelerat
ors. DNN-specific functional criticality analysis identifies faults that
cause measurable and significant deviations from acceptable requirements
such as the inferencing accuracy. This talk will examine the problem of cl
assifying structural faults in the processing elements (PEs) of systolic-a
rray accelerators. The speaker will first analyze the impact of stuck-at f
aults and present a two-tier machine-learning (ML) based method to assess
the functional criticality of these faults. The problem of minimizing misc
lassification will be addressed by utilizing generative adversarial networ
ks (GANs). The two- tier ML/GAN-based criticality assessment method leads
to less than 1% test escapes during functional criticality evaluation of s
tructural faults. While supervised learning techniques can be used to accu
rately estimate fault criticality\, it requires a considerable amount of g
round truth for model training. The speaker will therefore present a neura
l-twin framework for analyzing fault criticality with a negligible amount
of ground-truth data. A recently proposed misclassification-driven trainin
g algorithm will be used to sensitize and identify biases that are critica
l to the functioning of the accelerator for a given application workload.
The proposed framework achieves up to 100% accuracy in fault-criticality c
lassification in 16-bit and 32-bit PEs by using the criticality knowledge
of only 2% of the total faults in a PE.\n\nSpeaker Bio: \nKrishnendu Chak
rabarty has been at Duke University since 1998. His current research is fo
cused on: testing and design-for-testability of integrated circuits (espec
ially 3D SOC)\; microfluidic biochips\; hardware security\; neuromorphic c
omputing. His research projects in the past have also included digital pri
nt and enterprise system optimization\, chip cooling using digital microfl
uidics\, wireless sensor networks\, and real-time embedded systems. Resear
ch support is provided by the National Science Foundation\, DARPA\, Semi
conductor Research Corporation\, Air Force Research Labs\, Intel\, Synopsy
s\, and IBM. Other sponsors in the past have included the Army Research Of
fice\, National Institutes of Health\, Office of Naval Research\, Cisco\,
and HP.\n\nProf. Chakrabarty is a recipient of the 1999 National Science
Foundation Early Faculty (CAREER) Award\, the 2001 Office of Naval Researc
h Young Investigator Award\, the Mercator Professor award from Deutsche
Forschungsgemeinschaft\, Germany\, for 2000-2002\, and over a dozen best
paper awards at top conferences. He is a recipient of Duke University's 2
008 Dean's Award for Excellence in Mentoring\, and a recipient of the 2010
Capers and Marion McDonald Award for Excellence in Mentoring and Advising
\, Pratt School of Engineering\, Duke University. He was also awarded the
Distinguished Alumnus Award by the Indian Institute of Technology\, Kharag
pur\, in 2014. Prof. Chakrabarty has served as an ACM Distinguished Speake
r\, a Distinguished Visitor of the IEEE Computer Society\, and a Distingui
shed Lecturer of the IEEE Circuits and Systems Society. He is also a recip
ient of the Humboldt Research Award (2013) and the Humboldt Research Fel
lowship (2003)\, awarded by the Alexander von Humboldt Foundation\, Germa
ny. He holds 18 US patents and has several pending US patents. He served a
s Editor-in-Chief of IEEE Design &\; Test of Computers during 2010-20
12\, ACM Journal on Emerging Technologies in Computing Systems during 20
10-2015\, and IEEE Transactions on VLSI Systems during 2015-2018.\n\nPro
f. Chakrabarty received the B. Tech. degree from the Indian Institute of T
echnology\, Kharagpur\, India in 1990\, and the M.S.E. and Ph.D. degrees f
rom the University of Michigan\, Ann Arbor in 1992 and 1995\, respectively
\, all in Computer Science and Engineering . During 1990-95\, he was a r
esearch assistant at the Advanced Computer Architecture Laboratory of the
Department of Electrical Engineering and Computer Science\, University of
Michigan. During 1995-1998\, he was an Assistant Professor of Electrical a
nd Computer Engineering at Boston University.\n\n\n \;\n\n \n \nZoom I
nformation:\nJoin Zoom Meeting\nhttps://ufl.zoom.us/j/904047693\n\nMeeting
ID: 904 047 693\n\nOne tap mobile\n+16465588656\,\,904047693# US (New Yor
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by SIP\n904047693@zoomcrc.com\n\nJoin by H.323\n162.255.37.11 (US West)\n
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57.160 (Canada)\n207.226.132.110 (Japan)\nMeeting ID: 904 047 693\n\nJoin
by Skype for Business\nhttps://ufl.zoom.us/skype/904047693
ATTACH;FMTTYPE=image/jpeg:https://mestcenter.org/wp-content/uploads/2022/0
5/Krishnendu.jpg
CATEGORIES:Home Page,Webinars
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