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BEGIN:VCALENDAR VERSION:2.0 PRODID:-//wp-events-plugin.com//6.6.3//EN TZID:America/New_York X-WR-TIMEZONE:America/New_York BEGIN:VEVENT UID:174@mestcenter.org DTSTART;TZID=America/New_York:20221031T140000 DTEND;TZID=America/New_York:20221226T160000 DTSTAMP:20221013T221434Z URL:https://mestcenter.org/training/fundamentals-of-digital-ic-design/ SUMMARY:Fundamentals of Digital IC Design DESCRIPTION:Abstract:\nFull Understanding of the Digital IC Design Flow and the Entire Transformation\nProcess of Taking the Design from RTL to final bitstream on FPGA and GDSII on\nASIC. The course includes hands on traini ng on FPGA\, and final project Tapeout\nand fabrication on SKY130.\nCourse Description:\nDigital design flow is a lengthy process that involves many steps to take the design from RTL to\na working silicon. The objective of this course is to demystify this field and provide in-depth\nunderstandin g of the different transformations in each design step\, how these transfo rmations\ncan affect the final performance metrics\, and how to tune the p rocess to meet design specs.\n\nSpecifically\, this course focuses on fund amental elements in the design process\, including HDL\nmodeling\, event-d riven simulation\, synthesis\, timing analysis\, technology files\, standa rd cell\nviews\, physical design\, signoff checks\, and test planning. Thr oughout the course\, attendees learn\nthe salient differences in these ele ments when using FPGA and ASIC platforms. Both Xilinx (for\nFPGA) and Cade nce (for ASIC) design flows are utilized as part of the training vehicle. VIVADO\nfrom Xilinx to cover the entire FPGA flow. On the Cadence side\, A SIC simulations is\ndemonstrated using Incisive\, while Genus is used for synthesis\, and Innovus for physical\nimplementation. Finally\, Mentor Gra phics’ Calibre is used for ASIC signoff checks. The course\ncontains a d emonstration project\, which is progressively developed by the trainees th roughout the\ncourse modules to exercise the two digital design flows. The goal of this course is to provide\nattendees with understandings of FPGA and ASIC digital flows and to support this understanding\nwith hands-on ex perience of tools used by the industry.\nIntended Learning Outcomes (ILOs) :\nUpon the completion of this course\, trainees should be able to:\n H olistically understand digital design flow (from the specification phase t o the signoff\nchecks).\n Learn all transformations occur during the de sign flow and analyze their effect on\nperformance metrics.\n Gain know ledge on different technology files and standard cell views.\n Identify different design flows based on the target implementation technology (ASI C vs.\nFPGA).\n Understand timing-analysis and timing-closure in differ ent design phases.\n Understand chip level planning (Power Distribution Network\, IO\, Global Signals\, etc).\n Design simple digital blocks s tarting from RTL and taking them to Bitstream or GDSII.\nTarget Audience:\ nEntry-level design engineers who want to grasp the full digital design cy cle\, senior undergraduate\nand post-graduate students (who are preparing to get involved in digital IC design\, research and\ndevelopment\, hardwar e test)\, product and verification engineers as well as system and compute r\narchitecture engineers.\nCourse Details:\n- 32 hours – 8 weeks – 2- hr lectures twice a week\nCourse topics:\n- Module-I: Fundamentals (40%):\ no Digital vs Analog.\no Architecture of digital circuits (Delays\, data p ath\, control path\, synchronization\,\ndata encoding).\no Digital System Design (Microprocessors\, FPGA\, ASIC).\no Fundamentals of digital design (HDL modeling\, synthesis \, timing analysis and\ntiming closure\, physica l design\, chip planning\, signoff checks)\n\nHands-on Lab:\no Analyzing a nd comparing analog vs digital signals over oscilloscopes to\nunderstand t he analog side of digital signals (video demonstration).\no Building very simple processor to understand the fundamentals of digital design\nand the fundamentals of HDL.\n- Module-II: FPGA based design (25%):\no What is an FPGA?\no FPGA fabric architectures.\no HDL modeling and Synthesis for FPG A.\no FPGA types and applications (eFPGAs\, Hardware acceleration\, ASIC\n prototyping\, etc.).\n\nHands-on Lab:\no Synthesize a simple processor for FPGA and understand the resultant synthesized\nHDL and how FPGA bit strea m works.\no Detailed comparison between different FPGA fabrics based on ve ndors and\nfamilies.\n- Module-III: ASIC design (35%):\no Components of pr ocess design kits (PDKs).\no What are standard cells and standard cell vie ws?\no Types of digital synthesis.\no Timing analysis (STA\, SSTA).\no Phy sical design (floorplanning\, power planning\, Clock Tree Synthesis (CTS)\ , and\ntiming closure)\no Chip level planning (I/O\, power planning\, chip testing)\no Signoff checks (DRC\, LVS\, …)\no GDSII.\no Preparing for c hip testing\, Dos and Don’ts.\n\nHands-on Lab:\no Model a basic processo r for ASIC and understand HDL coding style for ASIC vs\nFPGA.\no Examine a ll the files in the design kit/standard cell views and understand the\ninf ormation provided in each file type.\no Synthesize the processor and under stand the different transformations occur with\neach design step.\no Imple ment the physical design and signoff check steps and generate the GDSII of \nthe processor.\nCourse Facilities:\nThroughout the course\, trainees wil l have access to the following computer software:\n- Access to VIVADO from Xilinx\; Incisive\, Genus\, Innovus\, from Cadence\, Modelsim and\nCalibr e from Mentor Graphics.\n- Access to SKY130 (PDK) that includes standard c ells library.\nCourse Perquisites:\n- Basic understanding of Digital Logic and Computer Architecture is preferable.\nCourse Instructor:\nProf. Eslam Tawfik is currently a research professor at The Ohio State University. Hi s research\ntopics focus on Digital SoC Design\, Hardware Security and Tru st\, Non Von-Neumann\nArchitecture\, Neuromorphic Computing\, Post-Quantum Cryptography\, Low-Power Resilient ICs\,\nHardware Emulation\, and CAD me thods. He has solid digital design experience targeting FPGAs\nand ASICs\, where he worked on different technology nodes to fabricate large number o f SoCs. He\nalso has solid teaching experience in digital design\, compute r engineering\, and computer science\ncurriculums.\n\nNOTE: This course wi ll take place only on Mondays and Thursdays (from 2-4 pm EST) within the date frame provided. \n \nZoom Information:\n CATEGORIES:Courses END:VEVENT BEGIN:VTIMEZONE TZID:America/New_York X-LIC-LOCATION:America/New_York BEGIN:DAYLIGHT DTSTART:20220313T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20221106T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST END:STANDARD END:VTIMEZONE END:VCALENDAR