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BEGIN:VCALENDAR VERSION:2.0 PRODID:-//wp-events-plugin.com//6.6.3//EN TZID:America/New_York X-WR-TIMEZONE:America/New_York BEGIN:VEVENT UID:155@mestcenter.org DTSTART;TZID=America/New_York:20201118T120000 DTEND;TZID=America/New_York:20201118T130000 DTSTAMP:20240901T193857Z URL:https://mestcenter.org/training/webinar-towards-secure-high-performanc e-computer-architectures/ SUMMARY:Webinar: Towards Secure High-Performance Computer Architectures DESCRIPTION:To watch the recorded webinar\, click on the recording.\nPlay V ideo \nSpeaker:\nDr. Srini Devadas\, Webster Professor of Electrical Engi neering and Computer Science at MIT\nAbstract:\nDigital design flow is a l engthy process that involves many steps to take the design from RTL to the system testing phase. The objective of this webinar is to demystify this field and provide in-depth understanding of the different transformations that occur in each design step\, and how these transformations can affect the final performance metrics. The webinar will focus on FPGAs as the targ et technology. FPGA is a very powerful technology to implement complex Sys tem on Chip (SoCs) in an efficient way and in extremely fast time to marke t. With the recent advancements in their architecture\, speed\, power effi ciency\, and peripherals\, FPGAs breached almost every field from IoT to s pace and military applications.Specifically\, this webinar will focus on f undamental elements in the design process\, including HDL modeling\, event ‑driven simulation\, synthesis\, timing analysis\, and FPGA architecture .\nSpeaker Bio:\nSrini Devadas is the Webster Professor of Electrical Engi neering and Computer Science and has has been on the MIT EECS faculty sinc e 1988. He served as Associate Head of the Department of Electrical Engine ering and Computer Science\, with responsibility for Computer Science\, fr om 2005 to 2011.\n\nDevadas's research interests span Computer-Aided Desig n (CAD)\, computer security and computer architecture and he has received significant awards from each discipline. In 2015\, he received the ACM/IEE E A. Richard Newton Technical Impact award in Electronic Design Automation . He received the IEEE Computer Society Technical Achievement Award in 201 4 for inventing Physical Unclonable Functions and single-chip secure proce ssor architectures. Devadas's work on hardware information flow tracking p ublished in the 2004 ASPLOS received the ASPLOS Most Influential Paper Awa rd in 2014. His papers on analytical cache modeling and the Aegis single-c hip secure processor were included as influential papers in "25 Years of t he International Conference on Supercomputing." In 2017 he received the IE EE W. Wallace McDowell Award for contributions to secure hardware. He is a n IEEE and ACM Fellow.\n\nDevadas has taught widely in EECS\, lecturing cl asses in VLSI\, discrete mathematics\, computer architecture\, algorithms and software engineering. He is a MacVicar Faculty Fellow and an Everett M oore Baker teaching award recipient\, considered MIT's two highest undergr aduate teaching honors. \n \nZoom Information:\nJoin Zoom Meeting\nhttps:/ /ufl.zoom.us/j/904047693\n\nMeeting ID: 904 047 693\n\nOne tap mobile\n+16 465588656\,\,904047693# US (New York)\n+16699006833\,\,904047693# US (San Jose)\n\nDial by your location\n+1 646 558 8656 US (New York)\n+1 669 900 6833 US (San Jose)\nMeeting ID: 904 047 693\nFind your local number: https ://ufl.zoom.us/u/ab5VOI6m6G\n\nJoin by SIP\n904047693@zoomcrc.com\n\nJoin by H.323\n162.255.37.11 (US West)\n162.255.36.11 (US East)\n221.122.88.195 (China)\n115.114.131.7 (India Mumbai)\n115.114.115.7 (India Hyderabad)\n2 13.19.144.110 (EMEA)\n103.122.166.55 (Australia)\n209.9.211.110 (Hong Kong )\n64.211.144.160 (Brazil)\n69.174.57.160 (Canada)\n207.226.132.110 (Japan )\nMeeting ID: 904 047 693\n\nJoin by Skype for Business\nhttps://ufl.zoom .us/skype/904047693 ATTACH;FMTTYPE=image/jpeg:https://mestcenter.org/wp-content/uploads/2022/0 8/SD.png CATEGORIES:Home Page,Webinars END:VEVENT BEGIN:VTIMEZONE TZID:America/New_York X-LIC-LOCATION:America/New_York BEGIN:STANDARD DTSTART:20201101T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST END:STANDARD END:VTIMEZONE END:VCALENDAR