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M1.J: Probing-Aware Bitstream Generation with ShuFFle

May 1, 2022 by Harry Monkhorst


Objective: The learning objective of this module is for trainees to gain hands-on experience on how to protect an FPGA-based design from probing attacks through the Probing-Aware Bitstream Generation (PABG) software tool. Trainees will apply the ShuFFle method, which is the central technique incorporated in PABG, to an example RTL design while taking it through a typical FPGA toolflow. The end result of using PABG will be a bit file that is used to program the probing-resilient design onto a particular FPGA chip. Additionally, an optional experiment to verify fundamental concepts in hardware is presented.

Target Audience: Government officers, Scientists

Prerequisite Knowledge and Skills:

  • programming knowledge: Verilog HDL, Python
  • Xilinx Vivado softwares
  • A FPGA board experience

Resources Provided at the Training | Deliverables:

  • Detailed description of set-ups used in training
  • A video demo of the module
  • Python scripts examples for analysis

Learning Outcome: In this module, we took an example RTL design and passed it through the Probing-Aware Bitstream Generation (PABG) toolflow, using the ShuFFle technique. This provided a hands-on experience in incorporating cutting-edge defensive techniques into the FPGA synthesis and implementation process, ultimately helping to protect a design from probing attacks. The end result of this procedure was a bit file used to program the probing-resilient design onto a particular FPGA chip. Subsequently, the optional hardware experiment provided a visual insight that confirmed important assumptions behind the ShuFFle technique.

 

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