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Webinar on November 06, 2019, 12:00 PM Eastern Time (US & Canada)
Presenter: Dr. Eslam Tawfik, The Ohio State University
Digital design flow is a lengthy process that involves many steps to take the design from RTL to the system testing phase. The objective of this webinar is to demystify this field and provide in-depth understanding of the different transformations that occur in each design step, and how these transformations can affect the final performance metrics. The webinar will focus on FPGAs as the target technology. FPGA is a very powerful technology to implement complex System on Chip (SoCs) in an efficient way and in extremely fast time to market. With the recent advancements in their architecture, speed, power efficiency, and peripherals, FPGAs breached almost every field from IoT to space and military applications.
Specifically, this webinar will focus on fundamental elements in the design process, including HDL modeling, event‑driven simulation, synthesis, timing analysis, and FPGA architecture.