Modules

Description

Learning modules are available only to MEST members.

To access these modules, you must be logged in to your nanoHUB account, and a MEST group membership is required.

Target Audience: Designed for U.S. citizens working in the Department of War, Government, or Government-affiliated employees, industry, as well as college students and faculty. To gain access to the materials, please ensure you have a nanoHUB account registered with your organizational email and follow these steps:

1. Create a nanoHUB account at https://nanohub.org/register/.

2. Request membership in the MEST group at https://nanohub.org/groups/mest.

Your feedback matters! Help us gain a better understanding of your learning experience. We invite you to complete the short pre-module survey before you access any of the modules and the short post-module survey after completing the modules. Thank you.

Pre-module Survey

Post-module Survey

PUF Design

M07 – Physical Unclonable Function (PUF) (Simulation)

M32 – Introduction to Physical Unclonable Functions

M33 – PUF Statistics

M34 – NIST Statistical Tests for PUFs

M35 – PUF Classes and Applications

M36 – PUF Architectures I

M37 – RO PUF Implementation I

M52 – RO PUF Implementation II

M53 – RO PUF Implementation III

M54 – RO PUF Implementation IV

M58 – PUF Architectures II

M59 – PUF Architectures III

M83 – PUF-Based Authentication: Introduction to Authentication

M84 – PUF-Based Authentication: Transport Layer Security

M85 – PUF-Based Authentication: Introduction to PUF-Based Authentication Protocols

M86 – PUF-Based Authentication: Overview of Fuzzy Extractors

M87 – PUF-Based Authentication: Recently Proposed PUF-based Authentication Protocols

M107 – PUF-Based Authentication: Advanced, Lightweight, Privacy-Preserving PUF-Based Authentication Protocols

TRNG Design

M57 – RO based TRNG

M76 – Introduction to TRNGs

M77 – Unified PUF-TRNG Architectures

M78 – TRNG Statistics

SoC Verification

M55 – Basics of verification

M48 – Property based Security Verification

M51 – System level verification using SystemC-UVM

M104 – Introduction to Simulation-based Hardware Fuzzing

SoC Design

M46 – Intro to SoC – Basic SoC Arch

M47 – Intro to SoC – Interconn and Sys Integration

M22 – Introduction to SoC Modeling with Platform

M68 – Introduction to PetaLinux – Embedded Operating Systems

M69 – Introduction to Systems-on-Chip: Multi-Processor Integration

AI/ML

M42 – Overview of Machine Learning

M43 – Domain Specific ML in Microelectronic Field

M44 – Introduction to Large Language Models (LLMs)

M45 – Introduction To IEA-Plot

M75 – Unsupervised Learning

UAV Systems

M28 – Introduction to UAVs

M29 – Hardware Security of Drones

M30 – UAV Cybersecurity

M31 – Digital Twin of UAV Hardware

M72 – Anti-Drone Systems: Components and Designs

M73 – UAV Programming: Environment Setup

M81 – UAV Programming: Programming Exercises

M82 – UAV Security Assessment

Logic Locking

M09 – Logic Locking Insertion and Assessment

M02 – Optical Probing Assessment on Logic Locking

M24 – Different Locking Schemes For Preventing IP Piracy I

M25 – Basics of Boolean Satisfiability Analysis

M26 – Boolean Satisfiability (SAT) Attack with tool demo on Logic Locking

M27 – SAT Attack Complexity Analysis

M70 – SAT Attack-based Simple Test Pattern Generation Approach

M71 – SAT Attack-based Complex Test Pattern Generation and Identification of Redundant Faults

Asynchronous Systems

M38 – Overview of Asynchronous Logic Circuits and Their Applications in Microelectronics Security and Reliability

M39 – Asynchronous Logic Circuit Design for Extreme Temperatures

M40 – Asynchronous Logic Circuit Design for Radiation Hardening

M41 – Asynchronous Logic Circuit Design for Side-Channel Attack Resilience

M79 – Asynchronous Polymorphic Circuits for Hardware SecurityM79 – Asynchronous Polymorphic Circuits for Hardware Security

M80 – Asynchronous Polymorphic Circuits for Hardware Security – A Case Study

M88 – Design Automation of MTNCL Asynchronous Circuits

M89 – Asynchronous RESet (ARES) PUF

Hardware Trojan

M04 – Hardware Trojan Insertion and Detection

M15 – Hardware Trojan Detection in ICs Using SEM Images

Recycled IC Detection

M01 – Recycled FPGA Detection

M13 – Recycled Chip Detection Using RO-based Odometer

M92 – Detecting Recycled Chips Leveraging the Aging Induced Biases in Memory Cells

M93 – A Self-referencing Approach Using Memory Power-up States for Detecting COTS SRAMs

Counterfeit Detection: imagei

M16 – Counterfeit IC detection using Optical Imaging

M18 – Counterfeit PCB Detection Using Optical Imaging I

M19 – Counterfeit PCB Detection Using Optical Imaging II

M20 – Counterfeit PCB Detection Using X-ray Imaging

IC Imaging

M14 – Scanning Electron Microscope Training

M17 – X-ray 3D Tomography Training

M21 – Near-field Terahertz Imaging

M67 – X-ray Tomography Applications for Electronics

Fault Injection

M49 – Detection of Fault Injection Attacks Using TDC Sensor

M56 – Fault Injection Attack on AES Chipher

M61 – Security Property Development and Fault-Injection Simulation

Micro-architectural Attack

M50 – Cache-based Micro-architectural Attacks (Possible Issues)

eFPGA based runtime monitoring

M60 – Security Policy Definition and eFPGA Implementation for AES Denial-of-Service (DoS) and Information Leakage Vulnerabilities

Cryptographic Hardware

M98 – Introduction to Cryptography

Hardware Emulation

M64 – Hardware Emulation based Fault Injection Assessment

M65 – Introduction to Hardware Emulation

M105 – Lab: Introduction to Emulation-Based Fuzzing

IoT Hardware Security

M94 – Robust, Low-Cost and Secure Authentication Scheme for IoT Applications

LLM

M63 – Security Question-Answering Framework through Retrieval Augmented Generation

M74 – Origin of Language Models – Self-Supervised Learning

M91 – From Prompts to AI Agents

LLM in SoC Security

M62 – Hardware Bug Detection using Large Language Model

M63 – Security Question-Answering Framework through Retrieval Augmented Generation

M99 – LLM-Driven Automatic Testbench Generation for RTL Security Bug Detection

M100 – Security Property and SystemVerilog Assertion Generation using LLM

M101 – Automated Threat Modeling and Test Plan Generation for Hardware Security

M103 – Hardware Asset Identification using Large Language Model

M106 – Best Practices for LLM-Generated HDL

Resolution Systems

M66 – Resolution and Texture

Runtime Monitoring

M102 – Introduction to Hardware Runtime Monitoring

Security Primitives

M77 – Unified PUF-TRNG Architectures

Side-channel Systems

M95 – Introduction to Side-Channels

M96 – Side-channel Attacks: Hands-on Experience

M97 – Side-Channel Attack Countermeasures