Objective: Recycled integrated circuits (ICs) are removed from scrapped printed circuit boards (PCBs) and their packages are “blacktopped” and/or remarked so that they can be sold as new parts. This module introduces IC aging phenomena and IC recycling, discusses modern FPGA look-up table (LUT) structure and usage, and provides a basic understanding of how to accurately detect recycled FPGAs in supervised and unsupervised classification scenarios by measuring LUT path delays from ring oscillators (ROs) programmed as macros into the FPGAs.
Target Audience: Government officers, Scientists
Prerequisite Knowledge and Skills:
- basic programming (Verilog HDL), MATLAB
- A FPGA board experience
Resources Provided at the Training | Deliverables:
- Detailed description of set-ups used in training
- A video demo of the module
- Verilog and MATLAB scripts examples for analysis
Learning Outcome: By end of this course trainees will understand the how to accurately detect recycled FPGAs in supervised and unsupervised classification scenarios by measuring LUT path delays from ring oscillators (ROs) programmed as macros into the FPGAs.