Objective: One of the key circuits in SoC security is physical unclonable function (PUF). PUFs are often used as chip IDs for various purposes as well as cryptography and coding. Various traditional approaches will be discussed including advantages and drawbacks in terms of both efficiency and stability. The learning objective of this module is for trainees to gain hands on experience with Physically Unclonable Functions (PUFs). Trainees will learn the properties of PUFs and some evaluation techniques. Trainees will be able to understand the meaning of different key PUF metrics, stabilization techniques, and the effects of variations.
Target Audience: Government officers, Scientists
Prerequisite Knowledge and Skills:
- programming knowledge: Verilog HDL
- Cadence Jaspergold, Xilinx Vivado softwares and FPGA board experience
- basic knowledge of AES cipher
Resources Provided at the Training | Deliverables:
- Detailed description of set-ups used in training
- A video demo of the module
- Verilog, python scripts examples for analysis
Learning Outcome: This lab introduces trainees to the fundamentals of PUFs and demonstrates a few of the measurements/evaluation techniques used to characterize PUFs. By the end of this course and experiment, trainees should understand the effects of PVT variations on PUFs, the necessity for stabilization/post-processing techniques, and the meaning of several key PUF metrics (native instability, bit error rate, intra- and inter-HD).