Objective: Hardware verification is performed at each stage of the design process, and it ensures that the model at hand adheres to the specifications defined by the customer. The learning objective of this module is for trainees to gain hands-on experience on the verification of a pre-silicon hardware design. Trainees will learn how to use industry-standard verification tools to build a secure design. We demonstrate two verification methodologies using two different tools: Klee and JasperGold. One demonstrates how to formally verify an RTL implementation of the Montgomery ladder algorithm (used in RSA encryption module) by property-checking. The other shows the test generation for Trojan identification in an RTL implementation of an AES design.
Target Audience: Government officers, Scientists
Prerequisite Knowledge and Skills:
- programming knowledge: Verilog HDL
- Cadence JasperGold formal verification tool
- basic knowledge of AES and RSA
Resources Provided at the Training | Deliverables:
- Detailed description of set-ups used in training
- A video demo of the module
- SystemVerilog, python scripts examples for analysis
Learning Outcome: This lab introduces trainees to the verification of a pre-silicon hardware design. By the end of this course, trainees will learn how to use industry-standard verification tools to build a secure design.