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Webinar: Securing Neural Networks Against Side-Channel Attacks with Hardware Masking

February 16, 2022 by Harry Monkhorst

Date/Time
Date(s) - 02/16/2022
12:00 PM - 1:00 PM
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To watch the recorded webinar, click on the recording.

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Speaker: 

Dr. Aydin Aysu, North Carolina State University

Abstract:

Intellectual Property (IP) thefts of trained machine learning (ML) models through side-channel attacks on inference engines are becoming a major threat.  Indeed, several recent works have shown reverse engineering of the model internals using such attacks, but the research on building defenses is largely unexplored.  There is a critical need to efficiently and securely transform those defenses from cryptography to ML frameworks.  A common defense technique is called masking, which randomizes all intermediate computations while preserving the same functionality.  Although masking is well-known for cryptography its extension to ML is non-trivial.  In this talk, I will explain different mechanisms to mask neural networks in hardware and describe related opportunities and challenges.  I will first discuss how a straightforward masking adaptation leaks side-channel information on neural networks and how to address this vulnerability.  I will then describe a fundamentally new approach that redefines neural networks to make them easier to mask in hardware.

Speaker Bio:
Dr.  Aydin Aysu is currently an assistant professor and Bennett Faculty Fellow at the Electrical and Computer Engineering Department of North Carolina State University, where he leads HECTOR: Hardware Cybersecurity Research Lab.  He got his M.S from Sabanci University in Istanbul, Turkey, and his Ph.D. from Virginia Tech. Before joining NC State, he was a post-doctoral researcher at the University of Texas at Austin.  Dr. Aysu‘s interests are broadly on hardware security research and cybersecurity education.  He has won the 2019 NC State Faculty Development Award, 2019 NSF Research Initiative (CRII) award, the 2020 Bennett Faculty award, and the 2020 NSF CAREER award.  His papers have been nominated for the best paper award both at 2018 and 2019 IEEE HOST conferences and have won the best paper award at 2019 GLS-VLSI and 2020 DATE conferences.  He is an IEEE senior member.


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