Date(s) - 11/06/2019
12:00 - 13:00
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Dr. Eslam Tawfik, Ohio State University
Digital design flow is a lengthy process that involves many steps to take the design from RTL to the system testing phase. The objective of this webinar is to demystify this field and provide in-depth understanding of the different transformations that occur in each design step, and how these transformations can affect the final performance metrics. The webinar will focus on FPGAs as the target technology. FPGA is a very powerful technology to implement complex System on Chip (SoCs) in an efficient way and in extremely fast time to market. With the recent advancements in their architecture, speed, power efficiency, and peripherals, FPGAs breached almost every field from IoT to space and military applications.Specifically, this webinar will focus on fundamental elements in the design process, including HDL modeling, event‑driven simulation, synthesis, timing analysis, and FPGA architecture.
Tawfik arrived at ESL after serving as an assistant professor at Benha University, Egypt. He earned his Ph.D. in micro-nano electronics from INPG, Grenoble, France, and his master’s and bachelor’s degrees from Benha University, Egypt, in microelectronics and data security. Along with various academic positions at leading international universities, including Zewail City of Science, Egypt, and The American University in Cairo, Tawfik held research engineering roles at the Information Technology Institute (ITI) and Mentor Graphics.
At ESL, Tawfik leads the Secure Microelectronics and Artificial Intelligence Circuits (SMART) Lab.
Bookings are closed for this event.