Course Details
July 6, 2026 – July 30, 2026
4 WEEKS | 12 HOURS
9:00 AM – 10:30 AM ET
Mondays and Thursdays
Course Description
Preliminary topics to cover (Can be subject to change)
The Increased value of packaging. STCO, Architecture, and Systems
Establishes system-level co-design methodologies and architectural frameworks spanning applications, circuits, and device physics. Key topics include monolithic IP disaggregation (logic, analog, SRAM), Known Good Die (KGD) yield validation, near-memory coupling, and the structural roadmap of High-Bandwidth Memory (HBM3 to HBM4). Engineers will build analytical models to resolve critical physical bottlenecks, focusing on sub-volt Power Delivery Networks (PDN), backside power delivery (BSPDN), hot-spot formation, and thermomechanical isolation.
Session 1: Packaging Evolution, Post-Moore Scaling, and the STCO Hierarchy
Introduces the transition of microelectronic packaging from traditional passive encapsulation to a primary driver of system performance, mapping this evolution directly to the System Technology Co-Optimization (STCO) framework. Participants will examine the historical migration from wire-bonding and pin-grid arrays to flip-chip and chiplet topologies, analyzing how cross-layer co-design across applications, circuits, devices, and materials mitigates the physical and economic limitations of single-node scaling to optimize Power, Performance, Area, and Cost (PPAC) at the system level.
Session 2: Workload/Use Case Driven Architectures (AI, HPC, 5G/6G)
Explores how domain-specific hardware requirements dictate advanced packaging implementations for generative AI clusters, high-performance computing (HPC), and next-generation communication networks. The session covers architectural adaptations required to support low-latency near-memory paths, massive parallel processing arrays, and the stringent insertion loss and electromagnetic isolation boundaries governing high-frequency 5G/6G RF packaging.
Session 3: Chiplet Philosophy & IP Disaggregation
Establishes the technical methodologies for decomposing monolithic System-on-Chips (SoCs) into specialized, modular chiplets or “cachelets.” Participants will investigate the structural, electrical, and macroeconomic trade-offs associated with partitioning logic, SRAM, and analog/PHY IPs across heterogeneous process nodes, alongside industry strategies for optimizing advanced packaging yield and validating Known Good Die (KGD).
Session 4: Memory Wall & Tighter Memory-Logic Coupling
Inspects the physical and architectural boundaries of the von Neumann bottleneck confronting next-generation compute systems. The lecture analyzes the latency, energy-per-bit, and shoreline routing constraints of traditional memory disaggregation, contrasting them with the high-bandwidth performance advantages of direct near-memory configurations, localized interconnect routing, and vertically stacked “Cache DRAM” topologies.
Session 5: High-Bandwidth Memory (HBM) Evolution
Provides an in-depth engineering analysis of the structural, electrical, and interface roadmaps from HBM3/3E to HBM4 architectures. Participants will evaluate the mechanical and electrical challenges of vertical Through-Silicon Via (TSV) configurations, the structural shift from microbump interconnects to fine-pitch hybrid bonding, and the architectural scaling from 1,024-bit to 2,048-bit wide I/O base die architectures.
Session 6: 3D Heterogeneous Integration: Logic, Memory, Analog, and RF
Details the vertical stacking of fundamentally incompatible process technologies within a true 3D integrated circuit (3DIC). The course material explores the design rules, substrate interfaces, and electromagnetic isolation techniques required to prevent high-speed digital switching noise from disrupting sensitive high-frequency analog, memory, and RF components co-located within the 3D stack.
Session 7: Advanced Power Delivery Networks (PDN)
covers the implementation of robust in-package power distribution mechanisms designed to sustain extreme sub-volt current densities while minimizing transient IR drop. The session focuses on the mechanics of back-side power delivery networks (BSPDN), the integration of nano-TSVs, the placement of on-die deep trench capacitors, and the deployment of integrated voltage regulators (IVRs).
Session 8: Thermal Extraction & Thermomechanical Isolation
Examines the severe thermomechanical limits and heat dissipation requirements associated with high-power density multi-die and 3D stacked systems. Participants will study the physics of localized hot-spot formation, the properties of advanced thermal interface materials (TIMs), microfluidic active cooling architectures, and layout methodologies for isolating sensitive memory tiles from adjacent high-heat compute cores.
Course Prerequisites
No prior experience in advanced IC packaging or assembly is required.
Target Audience
This course is designed for electrical engineers, materials scientists, mechanical engineers, and manufacturing professionals involved in the design, fabrication, and testing of integrated circuits (ICs). It is also highly relevant for technical managers and supply chain professionals in the semiconductor industry.
Registration
Registration is open!
Mohamed Arafa
Course Instructor
Dr. Mohamed Arafa was a Research Fellow at Natcast, where he focused on System and Technology Co-Optimization (STCO) and next-generation memory technologies. He brings over three decades of R&D experience, including a distinguished career at Intel Corporation, where he led system-level architecture initiatives spanning memory, packaging, and platform development—contributing to key technologies such as Intel® Optane™ Persistent Memory and the Xeon CPU platforms.
Dr. Arafa earned his Ph.D. in Electrical Engineering from the University of Illinois at Urbana-Champaign, with research in quantum-confined devices, strained silicon, and RF metrology. He also holds an MBA in High-Technology Management from the W. P. Carey School of Business at Arizona State University. His academic experience includes teaching and program development as an adjunct professor at ASU and a visiting professor at the American University of Sharjah, where he helped align engineering education with industry needs.
He has authored numerous technical publications, holds multiple patents, and has played a pivotal role in academia-industry collaboration through the Intel Research Council and the Semiconductor Research Corporation (SRC).
Areas of Expertise: Expert in semiconductor technology strategy, advanced memory and packaging integration, and system technology co-optimization bridging research, industry, and policy.