Dates
Feb 09, 2026 – Feb 12, 2026
4 days
Class Days
Monday – Thursday
Meeting Times
10:00 AM – 5:00 PM ET
28 Hours | 7 hours of lectures per day
Course Description
This course offers a comprehensive introduction to hardware emulation, suitable for both engineers who are new to the field and those seeking a structured refresher. It begins with the fundamental concepts and architecture of hardware emulation, providing a solid foundation for understanding how emulation fits into modern verification flows.
Participants will gain hands-on insight into preparing RTL designs and testbenches for emulation platforms, executing compilation and emulation flows, and effectively debugging complex verification environments. The course also explores advanced applications such as in-circuit emulation, co-emulation, and software validation. Through real-world case studies, attendees will learn how emulation is used in industry today and gain perspective on emerging trends and future directions in emulation technology.
What You Will Learn
By the end of this course, participants will be able to:
- Understand the core principles and benefits of hardware emulation
- Describe emulation architecture and system components
- Prepare RTL designs for deployment on emulation platforms
- Develop and adapt testbench strategies for emulation
- Execute compilation, emulation, and debug workflows
- Apply in-circuit emulation (ICE) and co-emulation techniques
- Implement hybrid verification and validation workflows
- Optimize emulation performance
- Manage emulation infrastructure and resources
- Analyze real-world case studies and practical applications
- Understand current trends and future directions in emulation technology
Course Prerequisites
Attendees should have experience in RTL design and simulation-based verification for digital semiconductors, including familiarity with SystemVerilog/Verilog. Some level of programming experience in C/C++ is helpful but not required.
Student requirements: Internet access during the entire class
Target Audience
Designed for U.S. citizens working in the Department of War, Government, or Government-affiliated employees, industry, as well as college students and faculty. Must register with your organizational email, and will be notified of acceptance within one week of the course start date.
Registration
Registration is open!
B. Wade Hostler (Wade)
Course Instructor
B. Wade Hostler (Wade) is a 30-year veteran in the EDA industry and has worked with digital semiconductor design and verification for 40 years. He has worked with hardware-assisted verification tools during the course of his entire career from early hardware acceleration tools such as Daisy and Zycad to the latest in hardware emulation. Although his primary focus has been in digital verification he has also participated in many other aspects of digital semiconductor design including RTL design, cell library creation for layout, design capture, and verification, place and route, and DFT/wafer probe.