Date/Time
Date(s) - 02/25/2026
12:00 PM - 1:00 PM
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Speaker
Dr. Jim Plusquellic is a professor in the Electrical and Computer Engineering Department at the University of New Mexico and President and CEO, IC-Safety.
Abstract
A hardware-obfuscated secure enclave (HOSE) chiplet is described for providing hardware-based security functions within 2.5D and 3D packages. The HOSE incorporates a physical
unclonable function (PUF) called the Shift-Register Reconvergent-Fanout (SiRF) PUF-TRNG for generating encryption keys, authentication bitstrings, and nonces, for securing communication between chiplets within the package and across components of the sytem architecture. Two embedded instruments are incorporated within the HOSE, namely, a time-to-digital converter (TDC) for providing high resolution path delay measurements, and a voltage-to-digital converter (VDC) for measuring power supply AC and DC side-channel signals. The instruments provide several novel security-related capabilities, e.g., they can be used for detecting power grid anomalies introduced by malicious computing and/or probing activities, for detecting replacements to chiplet components within the package, and for implementing a package-level PUF architecture.
The HOSE chiplet also includes an embedded FPGA component to enable the implementation of a novel secure boot process, and for implementing an advanced form of side-channel resistance for encryption algorithms. The re-programmability of the embedded fabric will also support crypto-agility, i.e., upgrades to cryptographic algorithms that run within the HOSE chiplet, including the instantiation of post-quantum resistant cryptographic algorithms.
Biography
Professor Plusquellic received both his M.S. and Ph.D. degrees in Computer Science from the University of Pittsburgh in 1995 and 1997, respectively. He is currently a Professor in Electrical and Computer Engineering at the University of New Mexico. His research interests are in the area of nano-scale VLSI and include hardware-based security and trust, embedded system design, and package-level trust and assurance. Professor Plusquellic received an “Outstanding Contribution Award” from IEEE Computer Society in 2012 for co-founding and for his contributions to the Symposium on Hardware-Oriented Security and Trust (HOST), and again in 2017 from the Test Technology Technical Council for “For Outstanding Contribution as Co-Founder and General Chair of IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) in 2010”. He is Trust and Assurance Lead for ASU’s ME COMMONS (SWAP) Hub since July, 2024. He served as General Chair for HOST in 2010, as Program Chair for HOST 2008, 2009, and as Vice-Program Chair in 2020. He has served as Associate Editor for Transactions on Computers and is currently serving as Editor-in-Chief of Hardware Security for Cryptography, MDPI. He has been inducted into the HOST Hall-of-Fame and has authored or co-authored three book chapters for Springer Link. He received the “10 Years of Continuous Service Award” from the International Test Conference, a Best Paper Award from VTS, and an ACM Distinguished Service Award from SIGDA. He received the “Albuquerque lab-to-business accelerator” award in 2016, the “2014 Innovation Award” from the Science and Technology Center at the University of New Mexico, and has nearly 20 patents and provisional applications filed with the US. Patent and Trademark Office. Professor Plusquellic is President and CEO of IC-Safety, LLC and a consultant for Enthentica Inc., both start-ups in the hardware security and trust space. He has published more than 100 refereed conference and journal papers. He is a Senior IEEE member and a Golden Core Member of the IEEE Computer Society.
