AI-Enabled VLSI Testing​

Instructor 

Dr. Ujjwal Guin is a Godbold Associate Professor in the Department of Electrical and Computer Engineering at Auburn University.

Learning Objectives

VLSI testing is the process of detecting defects that typically occur during or after the manufacturing of integrated circuits (ICs). This hands-on course certificate introduces participants to AI-assisted VLSI testing, covering the integration of artificial intelligence across key stages of the testing process. Participants will explore AI-driven automatic test pattern generation, test pattern optimization and test point insertion. Through practical examples and guided activities, the workshop will demonstrate how AI can improve test efficiency, fault coverage, and automation in modern VLSI testing workflows.

VLSI testing seeks to identify manufacturing defects and ensure that fabricated integrated circuits operate according to their intended design specifications. Automatic Test Pattern Generation (ATPG) plays a central role in this process by generating input patterns that detect modeled faults within a circuit. In this course, we will discuss the foundational concepts of VLSI testing, explore AI-assisted test pattern generation, and examine machine learning-based approaches for test pattern optimization. Additionally, the course will explore how AI can complement conventional commercial ATPG tools by generating candidate patterns for hard-to-detect faults and reducing redundant test patterns while preserving fault coverage. The course includes a series of hands-on simulation and implementation exercises that provide practical experience with the key concepts discussed.

This course is divided into 3 modules:

• Unit 1: Basics of VLSI Testing: This section introduces the fundamentals of VLSI testing, including stuck-at fault models, fault detection, and basic ATPG, with hands-on test generation using Synopsys TestMAX.
• Unit 2: Automatic Test Pattern Generation Using AI: This section explains role of Artificial Intelligence (AI) in addressing the limitations of traditional ATPG test pattern generation techniques. This includes a demonstration on how AI models can assist in identifying hard-to-detect faults and< generating test input patterns that improve fault detection.
• Unit 3: AI-based Test Pattern Optimization: This section focuses on reducing the size and complexity of test sets while preserving fault coverage. Trainees will explore techniques for identifying redundant or low-value test patterns and selecting compact subsets of patterns using machine learning models.

Prerequisites:

• A basic understanding of circuits, logic gates, and VLSI testing is required.
• A basic understanding of Linux systems is recommended.
• Familiarity with machine learning concepts is helpful but not required.
• A basic knowledge of Tcl scripting is required.=
• Experience with commercial ATPG or EDA tools such as Synopsys TestMAX or TetraMAX is helpful but not required.

Target Audience

Designed for U.S. citizens working in the Department of War, Government, or Government-affiliated employees, industry, as well as college students and faculty. Must register with your organizational email and will be notified of acceptance within one week of the course start date

Biography

Ujjwal Guin is a Godbold Associate Professor in the Department of Electrical and Computer Engineering at Auburn University. He received his Ph.D. from the University of Connecticut in 2016. He is actively engaged in research projects spanning hardware security and trust, supply chain security, cybersecurity, and VLSI design and testing. He has developed several on-chip structures and techniques to enhance the security, trustworthiness, and reliability of integrated circuits. His contributions include authoring one book, two book chapters, thirty journal articles, and more than forty refereed conference papers. His research has been widely recognized through best paper nominations, awards, research grants, and prizes from various security competitions. Notably, one of his papers was referenced in the White House 100-Day Reviews under the EO 14017 report, specifically in the “Building Resilient Supply Chains” section, published in June 2021. Dr. Guin’s research projects are funded by the U.S. Army, the Air Force Office of Scientific Research (AFOSR), the Secret Service, the National Science Foundation (NSF), and the Air Force Research Laboratory (AFRL). He served on the technical program committees of several prestigious conferences, including DAC, ITC, HOST, VTS, PAINE, VLSID, GLSVLSI, ISVLSI, and Blockchain. He is currently the Technical Program Co-Chair of HOST 2025. He is a Senior Member of IEEE and ACM.