Date/Time
Date(s) - 03/26/2025
12:00 PM - 1:00 PM
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Speaker
Dr. Ujjwal Guin is a Godbold Associate Professor in the Department of Electrical and Computer Engineering at Auburn University.
Abstract
Reducing manufacturing defect escape in safety-critical applications demands higher fault coverage, yet achieving 100% fault coverage still remains a challenge. Concurrently, the hardware security community addresses logic locking to combat IP piracy by embedding locks in netlists, requiring correct key input for proper functionality. However, introduced in 2015, the SAT-based attack can efficiently recover secret keys no matter where the keys are placed in the netlist and break all existing logic-locking schemes. This talk focuses on (1) analyzing SAT attack complexity and (2) a novel SAT attack-driven test pattern generation method for logic circuits, treating stuck-at faults as locked gates with secret keys. This approach minimizes backtracking during the SAT attack, making it feasible to generate tests for hard-to-detect faults that are not detected by commercial ATPG tools.
Biography
Ujjwal Guin is a Godbold Associate Professor in the Department of Electrical and Computer Engineering at Auburn University. He received his Ph.D. from the University of Connecticut in 2016. He is actively engaged in research projects spanning hardware security and trust, supply chain security, cybersecurity, and VLSI design and testing. He has developed several on-chip structures and techniques to enhance the security, trustworthiness, and reliability of integrated circuits. His contributions include authoring one book, two book chapters, thirty journal articles, and more than forty refereed conference papers. His research has been widely recognized through best paper nominations, awards, research grants, and prizes from various security competitions. Notably, one of his papers was referenced in the White House 100-Day Reviews under the EO 14017 report, specifically in the “Building Resilient Supply Chains” section, published in June 2021. Dr. Guin’s research projects are funded by the U.S. Army, the Air Force Office of Scientific Research (AFOSR), the Secret Service, the National Science Foundation (NSF), and the Air Force Research Laboratory (AFRL). He served on the technical program committees of several prestigious conferences, including DAC, ITC, HOST, VTS, PAINE, VLSID, GLSVLSI, ISVLSI, and Blockchain. He is currently the Technical Program Co-Chair of HOST 2025. He is a Senior Member of IEEE and ACM.
