Date/Time
Date(s) - 11/19/2025
12:00 PM - 1:00 PM
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Speaker
Dr. Avinash Ayalasomayajula, Senior R&D Engineer, Caspia Technologies
Abstract
As hardware systems become increasingly complex, securing them during the design phase is more critical—and more challenging—than ever. Vulnerabilities introduced at this early stage, whether through oversight or intentional tampering, can lead to severe consequences such as intellectual property theft, system breaches, and operational failures. Traditional verification approaches often lack the precision and scalability needed to uncover subtle security flaws before silicon fabrication.
This webinar will delve into advanced techniques for pre-silicon security verification, emphasizing the need for automation to keep pace with modern development lifecycles. It will explore the role of formal property verification in identifying and mitigating hardware security risks, and how artificial intelligence can be harnessed to enhance this process.
Biography
Dr. Avinash Ayalasomayajula is a Senior R&D Engineer at Caspia Technologies, where he focuses on developing AI-driven tools for hardware security verification. He earned his Ph.D. in 2024 and M.S. in 2022 from the University of Florida. Under the mentorship of Dr. Farimah Farahmandi and Dr. Mark Tehranipoor, his doctoral research centered on applying formal property verification techniques to enhance pre-silicon hardware security. Avinash has published his work in leading venues including IEEE TCAD, IEEE MLCAD, and IEEE HOST.
