Design Automation of MTNCL Circuits

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Speaker 

Dr. Jia Di is the Head of the Electrical Engineering and Computer Science Department and is the Rodger S. Kline Endowed Leadership Chair at the University of Arkansas.

Abstract

As a quasi-delay insensitive (QDI) asynchronous logic paradigm, Multi-Threshold NULL Convention Logic (MTNCL), although much better than its synchronous counterpart, still has timing issues, which can only be addressed reliably through design automation, in contrast to manual adjustments for every case. This webinar will enumerate all four timing hazards of MTNCL circuits and describe the up-to-date work on design automation, along with results and comparisons.

Biography

Dr. Jia Di received B.S. and M.S. degrees from Tsinghua University, China, in 1997 and 2000, respectively. He completed his Ph.D. in Electrical Engineering at the University of Central Florida in 2004. He joined the University of Arkansas in Fall 2004, where he is now the Head of Electrical Engineering and Computer Science Department and Rodger S. Kline Endowed Leadership Chair. His research area is asynchronous integrated circuit design and hardware security. His Trustable Logic Circuit Design Lab has been sponsored by various federal agencies and industry for over $35M in the past twenty years. Dr. Di has published two books and over 130 papers on technical journals and conferences. He also has 7 U.S. patents. Dr. Di is a senior member of IEEE, an eminent member of Tau Beta Pi, and an elected member of the National Academy of Inventors.