Date/Time
Date(s) - 09/23/2026
12:00 PM - 1:00 PM
SpeakerĀ
Daniel DiMase is Founder & CEO of Aerocyonics, Inc. and Chair of the NDIA Electronics Division Trust & Assurance Committee.
Abstract
Counterfeit integrated circuit detection is frequently approached as a matter of applying a prescribed sequence of test methods. In practice, confidence in an assessment also depends on how effectively those methods address the relevant counterfeit defect population, how consistently laboratories execute and interpret the tests, and whether sufficient empirical evidence exists to quantify detection performance.
This webinar will review the counterfeit IC challenge and the continuing evolution of SAE AS6171, with emphasis on the relationship between standardized test methods, defect coverage, and risk-informed test selection. Lessons from multi-laboratory round-robin testing will be presented to illustrate the importance of representative test articles, established ground truth, laboratory proficiency, and consistent interpretation of test results.
The presentation will also introduce CVAT analytical tools for evaluating test-method coverage, laboratory observations, and counterfeit defect data. These capabilities provide a foundation for moving beyond binary pass/fail reporting toward more defensible assessments of detection confidence.
The webinar will conclude with a technical vision for future work, including validation of newly released AS6171 methods, expansion of representative counterfeit datasets, improved repeatability and defect-correlation metrics, AI-assisted image capture and anomaly analysis, and integration of decision-support capabilities into government and industry laboratory workflows. Broader implications for SAE G-32 microelectronics assurance activities will also be discussed.
Biography
Daniel DiMase is Founder & CEO of Aerocyonics, Inc. and Chair of the NDIA Electronics Division Trust & Assurance Committee. He has led standards, research, and implementation activities addressing counterfeit electronic parts, microelectronics assurance, supply-chain risk, and cyber-physical systems security.
His technical work includes AS6171-based test-method assessment, multi-laboratory validation, counterfeit defect-coverage analysis, data-driven test optimization, and the development of advanced microelectronics inspection and sample-preparation capabilities. He has also contributed to standards and assurance activities within the SAE G-19A and G-32 communities and works with government, industry, and academic organizations to transition emerging assurance technologies into practical use.
