Date/Time
Date(s) - 02/26/2027
10:00 AM - 2:00 PM
Instructors
Dr. Ujjwal Guin is an Associate Professor of Electrical and Computer Engineering at Auburn University, Aritri Priya Saha is a Ph.D. student in Electrical and Computer Engineering at Auburn University, Cooper Medved is an M.S. student in Electrical Engineering at Auburn University, and André Steffano Nava is an M.S. student in Electrical Engineering at Auburn University.
Abstract
This hands-on workshop introduces participants to AI-assisted VLSI testing, covering the integration of artificial intelligence across key stages of the testing process. Participants will explore AI-driven automatic test pattern generation, test pattern optimization, test point insertion, synthetic test data generation using Generative AI, and agentic AI systems for intelligent test generation. Through practical examples and guided activities, the workshop will demonstrate how AI can improve test efficiency, fault coverage, and automation in modern VLSI testing workflows.
Learning Objectives
At the end of the workshop, participants will be able to:
Workshop Outline
Target Audience
Designed for U.S. citizens working in the Department of War, Government, or Government-affiliated employees, industry, as well as college students and faculty. Must register with your organizational email, and will be notified of acceptance within one week of the course start date.
Course Details
Date: 26th February 2027
Time: 10:00 AM-2:00 PM ET
Location: Broun 311, Broun Hall, Auburn, and Synchronous over Zoom (Hybrid)
Biography
Dr. Ujjwal Guin is an Associate Professor of Electrical and Computer Engineering at Auburn University, where he holds the Godbold Associate Professorship. He received his Ph.D. from the University of Connecticut in 2016. His research spans hardware security and trust, supply chain security, cybersecurity, and VLSI design and test. He co-authored the book “Counterfeit Integrated Circuits: Detection and Avoidance,” two book chapters, over thirty journal articles, and forty refereed conference papers. His work has been cited in the White House “Building Resilient Supply Chains” report (June 2021) under EO 14017 and is sponsored by the U.S. Army, AFOSR, NSF, Secret Service, and AFRL. He serves on the TPCs of DAC, HOST, ITC, VTS, and others. He is General Chair of IEEE HOST 2027 — marking the conference’s 20th anniversary. He previously served as Program Co-Chair for ISVLSI 2026, HOST 2025, ATS 2024 and PAINE 2023. He is a Senior Member of IEEE and member of ACM.
Aritri Priya Saha is a Ph.D. student in Electrical and Computer Engineering at Auburn University in the Microelectronics Security Lab (MSL). Her research focuses on blockchain, distributed systems, semiconductor supply-chain security, and zero-knowledge proofs. As a technical contributor to the National Microelectronics Security Training Center (MEST), she has developed tools, experimental frameworks, and hands-on learning modules related to microelectronics security, testing, and trusted hardware systems. Her additional research interests include Boolean SAT-based VLSI testing frameworks and AI-assisted VLSI testing methodologies for improving testing efficiency and fault coverage.
Cooper Medved is an M.S. student in Electrical Engineering at Auburn University and a Graduate Research Assistant in the Microelectronics Security Lab (MSL). His research focuses on design-for-test, ATPG optimization, and FPGA hardware security. His current work includes developing scan-partitioning and AI-assisted ATPG techniques to improve test efficiency and reduce test application time while maintaining fault coverage. He also investigates security and reliability challenges in SRAM-based FPGAs, including configuration memory behavior and fault injection. His broader research interests center on improving the security, testability, and reliability of modern digital systems.
André Steffano Nava is an M.S. student in Electrical Engineering at Auburn University and a Graduate Research Assistant in the Microelectronics Security Lab (MSL). Advised by Dr. Guin, he began his research tenure in the lab as an undergraduate in January 2025 before transitioning to his graduate studies in December 2025. His research interests encompass hardware security, electronic design automation (EDA), and the detection and prevention of counterfeit microelectronics. Andre’s current research focuses on AI-based test point insertion, leveraging machine learning frameworks to optimize Automatic Test Pattern Generation (ATPG) methodologies. Furthermore, his work in hardware trust and security includes identifying and formally verifying system vulnerabilities, with specific expertise in analyzing Common Weakness Enumerations (CWEs) within Verilog and SystemVerilog designs.