Fundamentals of Chip-to-Chip Interconnect

Abstract

The course will go over the fundamental of digital system interconnect design, focusing on high level overview of the concepts, terminology and design challenges. Two communication modes will be discussed followed by a brief survey of popular standards and their transceiver architectures.

Instructor

Professor Tawfiq Musah (Senior Member, IEEE) received the B.S. degree in electrical engineering from Columbia University, New York, NY, USA, in 2005, and the Ph.D. degree in electrical and computer engineering from Oregon State University, Corvallis, OR, USA, in 2010.,He was with Intel Laboratories, involved in micro-power ADC design, from 2006 to 2007, and interned with Texas Instruments (TI), designing a hardware sensor, in 2010. From 2010 to 2018, he was with the Signaling Research Laboratory, Intel Corporation, Hillsboro, OR, involved on circuits and systems to enable Intel’s next generation chip-to-chip electrical and optical links. He is currently an Assistant Professor with the Department of Electrical and Computer Engineering, The Ohio State University, Columbus, OH, USA. His research interests include low-power equalization techniques for next-generation electrical and optical I/O links, multi-GS/s ADCs, and high-level circuit modeling and verification. Dr. Musah was a recipient of the Intel Labs Divisional Recognition Award in 2014 and 2017 and the Intel Laboratories Academy Award for Excellence in bringing new experiences or technical innovation to market in 2015.

Target Audience

Registration is open to DoD, Government, and Government-affiliated employees only.

Register with your organizational email and we’ll let you know about acceptance within one week prior to class start.

Course Details

February 12, 2024

Monday from 10:00 AM until 1:00 PM

Synchronous over Zoom

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