Fundamentals of Digital IC Design: From RTL to GDSII

Abstract

Full Understanding of the Digital IC Design Flow and the Entire Transformation Process of Taking the Design from RTL to final bitstream on FPGA and GDSII on ASIC. The course includes hands on training on FPGA, and final project Tapeout and fabrication on SKY130.

Course Description

Digital design flow is a lengthy process that involves many steps to take the design from RTL to a working silicon. The objective of this course is to demystify this field and provide in-depth understanding of the different transformations in each design step, how these transformations can affect the final performance metrics, and how to tune the process to meet design specs.
Specifically, this course focuses on fundamental elements in the design process, including HDL modeling, event-driven simulation, synthesis, timing analysis, technology files, standard cell views, physical design, signoff checks, and test planning. Throughout the course, attendees learn the salient differences in these elements when using FPGA and ASIC platforms. Both Xilinx (for FPGA) and Cadence (for ASIC) design flows are utilized as part of the training vehicle. VIVADO from Xilinx to cover the entire FPGA flow. On the Cadence side, ASIC simulations is demonstrated using Incisive, while Genus is used for synthesis, and Innovus for physical implementation. Finally, Mentor Graphics’ Calibre is used for ASIC signoff checks. The course contains a demonstration project, which is progressively developed by the trainees throughout the course modules to exercise the two digital design flows. The goal of this course is to provide attendees with understandings of FPGA and ASIC digital flows and to support this understanding with hands-on experience of tools used by the industry.

Target Audience

DoD, Government or Government Affiliated employees only. Must register with your organizational email and will be notified of acceptance within one week of course start date.

Entry-level design engineers who want to grasp the full digital design cycle, product and verification engineers as well as system and computer architecture engineers.

Course Details

September 16, 2024 – November 25, 2024 (Federal holiday on 11/11: no classes)

Mondays & Thursdays from 3PM until 5PM ET

Synchronous over Zoom

40 hours | 10 weeks | 2-hr lectures twice a week