Hardware Emulation-based Security Verification

Speaker 

Dr. Sujan Saha, University of Florida

Abstract

Hardware security verification is increasingly becoming a major bottleneck in modern System-on-Chip (SoC) development, particularly as designers face intense time-to-market pressure and rapidly expanding attack surfaces. Traditional simulation-based verification, while foundational, often struggles with performance limitations and poor scalability when evaluating complex SoCs for security verification. Hardware emulation platforms are emerging as a powerful alternative, offering orders-of-magnitude acceleration and new opportunities for comprehensive pre-silicon security validation.

This webinar will introduce the fundamentals of hardware emulation and highlight its advantages over conventional simulation techniques. We will demonstrate how emulation platforms, such as Synopsys ZeBu, can significantly accelerate security verification workflows. Key topics include emulation-driven hardware fuzzing to uncover known and unknown SoC vulnerabilities, pre-silicon fault-injection analysis for resilience evaluation, and strategies for scaling security testing to realistic workloads. We will also explore future directions, including integrating information-flow tracking into emulation environments and leveraging AI/LLM-based automation to further enhance coverage, efficiency, and insight.

Biography

Dr. Sujan Saha is a Postdoctoral Associate in the Department of Electrical and Computer Engineering at the University of Florida. He received his Ph.D. in Electrical and Computer Engineering from the University of Florida in 2023. He also holds an M.Sc. in Computer Engineering from the University of California, Riverside, and a B.Sc. in Electrical and Electronic Engineering from the Bangladesh University of Engineering and Technology (BUET). Dr. Saha’s research focuses broadly on System-on-Chip (SoC) security, with emphasis on FPGA-based embedded SoC security, the application of AI/LLMs to hardware security, hardware-assisted security verification, and runtime security monitoring. His scholarly contributions include a book chapter, a pending patent, and 40 peer-reviewed publications in leading venues such as DATE, ASP-DAC, HOST, ICCD, GLSVLSI, ISVLSI, AsianHOST, IEEE Design & Test, IEEE Access, ACM TRETS, and RTCSA. He has served on the technical program committees of IEEE HOST, GLSVLSI, and RTAS, and is a regular reviewer for journals including IEEE Access, TIFS, ACM Computing Surveys, Proceedings of the IEEE, and TCAD.