Hardware Security for Cryptography

Instructors 

Dr. Md Tauhidur Rahman, an Assistant Professor, Electrical and Computer Engineering, Florida International University, Miami, Florida, and Dr. Farimah Farahmandi, is the Wally Rhines Endowed Professor in Hardware Security in the Department of Electrical and Computer Engineering (ECE) at the University of Florida

Learning Objectives

Modern computing systems rely heavily on cryptographic hardware to provide secure communication, data protection, authentication, and system integrity across a wide range of applications. While cryptographic algorithms offer strong theoretical security, their hardware implementations remain vulnerable to practical attacks that exploit physical and structural weaknesses in the design. The Hardware Security of Cryptology micro-certificate provides a structured learning path through the principles, attack methodologies, and verification techniques used to assess and protect cryptographic hardware systems. Learners will explore implementation-level security challenges such as fault injection, side-channel leakage, formal property verification, and security policy enforcement, while also examining emerging cryptographic paradigms such as post-quantum cryptography. By combining foundational concepts with practical security analysis workflows, this course equips professionals to evaluate and strengthen modern cryptographic hardware implementations.

This course covers five major topics in five units described below:

• • Unit 1: Introduction to Cryptographic Hardware: This unit introduces the fundamental principles of cryptographic hardware and its role in securing modern computing systems. Learners explore the architectural foundations of hardware-based cryptographic modules, including symmetric and asymmetric cryptographic primitives, data flow, and key management mechanisms. The unit establishes the security-critical assets within cryptographic hardware and examines how implementation choices impact security, performance, and reliability. This foundation prepares learners to understand the attack surfaces and verification challenges addressed in the subsequent units.
  • Unit 2: Fault Injection Attacks on the AES Cipher: This unit focuses on fault injection as a practical attack methodology against cryptographic hardware implementations. Learners study how clock and voltage glitching can disrupt normal hardware behavior and induce exploitable faults during encryption operations. Through hands-on experimentation with AES hardware implementations, participants analyze fault behavior, observe security failures, and understand how implementation-level weaknesses can undermine cryptographic confidentiality. The unit provides practical insight into offensive hardware security evaluation and fault-based vulnerability analysis.
  • Unit 3: Property-Based Security Verification: This unit introduces formal property-based verification as a methodology for evaluating cryptographic hardware security during pre-silicon design stages. Learners identify security-critical assets, define threat models, and translate security requirements into formal properties and SystemVerilog Assertions (SVAs). Using formal verification workflows, participants analyze whether a cryptographic design adheres to its intended secure behavior. The unit emphasizes proactive vulnerability detection and demonstrates how formal verification techniques can strengthen hardware security assurance before deployment.
  • Unit 4: Security Policy Definition and eFPGA Implementations for AES Denial-of-Service and Information Leakage Vulnerabilities: This unit explores the development and implementation of security policies to detect and mitigate hardware security vulnerabilities in cryptographic modules. Learners examine practical vulnerability scenarios, including denial-of-service conditions and unauthorized information leakage, and define security policies to enforce expected secure behavior. The unit also introduces eFPGA-based policy implementation as a flexible hardware security mechanism, demonstrating how reconfigurable logic can support runtime detection and adaptive security enforcement in cryptographic systems.
  • Unit 5: Supplemental Lectures:
    • Accelerating the Post-Quantum Revolution – High-Performance Solutions for Tomorrow’s Cryptography: This lecutre examines the hardware implications of transitioning from classical cryptographic algorithms to post-quantum cryptographic standards. Learners explore the performance, scalability, and implementation challenges associated with post-quantum cryptographic schemes and the role of specialized hardware acceleration in enabling efficient deployment. The unit highlights emerging architectural approaches for accelerating quantum-resistant cryptographic operations while maintaining strong security guarantees, preparing learners to understand the evolving hardware requirements of future cryptographic systems.
    • Side Channel Leakage Assessment of Cryptographic Modules: This lecture focuses on evaluating cryptographic hardware for side-channel vulnerabilities that may leak sensitive information through physical observables such as timing or power behavior. Learners explore methodologies for identifying, quantifying, and analyzing side-channel leakage across different abstraction levels of hardware design. The unit emphasizes systematic leakage assessment and vulnerability localization, enabling participants to understand how side-channel analysis supports secure hardware design and how targeted countermeasures can improve implementation resilience.

Prerequisites:

• Basic understanding of digital hardware design, cryptographic concepts, and hardware security principles
• Familiarity with Register Transfer Level (RTL) design and hardware verification workflows
• Basic knowledge of cryptographic algorithms such as AES and their hardware implementations
• Prior exposure to FPGA-based design or hardware security evaluation techniques is helpful but not required

Target Audience

Designed for U.S. citizens working in the Department of War, Government, or Government-affiliated employees, industry, as well as college students and faculty. Must register with your organizational email, and will be notified of acceptance within one week of the course start date

Biography

Md Tauhidur Rahman is an Assistant Professor in the Department of Electrical and Computer Engineering at Florida International University (FIU). He obtained his Ph.D. in Computer Engineering from the University of Florida in 2017 (advised by Dr. Mark Tehranipoor). He is the recipient of NSF CRII and the director of the SeRLoP (Security, Reliability, Low-power, and Privacy) Research lab. His research interests include hardware security and trust, side-channel analysis, and embedded security. His research is funded by the National Science Foundation (NSF), the National Security Agency (NSA), the Department of Defense (DoD), and CyberFlorida.

Dr. Farimah Farahmandi is the Wally Rhines Endowed Professor in Hardware Security in the Department of Electrical and Computer Engineering (ECE) at the University of Florida. She also serves as the Associate Director of the Florida Institute for Cybersecurity (FICS) at the University of Florida. Her research focuses on hardware security verification, formal methods, fault-injection attack analysis, and post-silicon validation and debug, resulting in 7 books and over 140 publications in these fields. Dr. Farahmandi’s research has been sponsored by a variety of leading companies and government agencies. For her contributions, she is a recipient of 7 best paper and nomination awards, and was recognized with the ACM/IEEE DAC Under 40 Innovators Award (2024), the Best Assistant Professor Award at the University of Florida (2024), the Excellence in Service Award (2023), and the Excellence in Research Award (2022) from the ECE department at UF. She also received the prestigious Young Faculty Award from SRC (2022) and the NSF CAREER Award.