Hardware Trojans

Instructor 

Dr. Mark Tehranipoor, Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity and the Chair of the Department of Electrical and Computer Engineering (ECE) at the University of Florida and Dr. Navid Asadi is an Associate Professor in the Electrical and Computer Engineering Department at the University of Florida with an affiliation to the Materials Science and Engineering Department.

Learning Objectives

A hardware Trojan is a malicious modification to an integrated circuit (IC) that alters its intended behavior, often remaining dormant until triggered under specific conditions. These modifications can be introduced during various stages of the hardware design and fabrication process, especially when third-party IPs or untrusted foundries are involved. The presence of a Trojan can lead to severe consequences, including data leakage, denial of service, functionality degradation, or complete system compromise, particularly in security-critical applications. Trojan insertion methods include adding extra logic at the RTL or gate level, modifying existing logic, or exploiting unused circuit paths. These insertions can be stealthy and low overhead, making detection difficult. Detection methods range from functional testing, side-channel analysis (e.g., power or delay anomalies), formal verification techniques, and information flow tracking to machine learning-based classifiers trained to recognize abnormal patterns. Early detection and prevention of hardware Trojans are essential for maintaining trust and reliability in modern hardware systems. Hence, it is important to learn about hardware trojan detection methods to verify systems against trojan attacks and insertion methods to analyze the characteristics of trojans.

In this certificate course, students will learn about hardware trojans, how they can be inserted into a design, and two methods for detecting trojans: using formal methods and Integrated Circuit (IC) Imaging.

This micro-certificate course is organized into a set of units described below:

• Unit 1: Pre-silicon Trojan Insertion and Detection: Introduces hardware trojan with example, explains how trojans can be inserted in a design and how formal verification can be used to detect malicious modification or trojan.
• Unit 2: Post-silicon Trojan Detection: describes imaging techniques such as scan electron microscope (SEM) to detect hardware trojan or malicious modification in a fabricated chip.
• Unit 3: Research Series on Malicious Hardware: It contains two lectures (1) closing hidden backdoors that act as side channel to leak sensitive information, and (2) how to use laser probing to detect sequential trojan.

Prerequisites:

• A background in RTL design and C++ programming will be helpful.

Biography

Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity and the Chair of the Department of Electrical and Computer Engineering (ECE) at the University of Florida. He is also currently serving as the Director for Florida Institute for Cybersecurity (FICS) Research, Director for Edaptive Computing Inc. Transition Center (ECI-TC), Co-director for the AFOSR/AFRL Center of Excellence on Enabling Cyber Defense in Analog and Mixed Signal Domain (CYAN), and Co-Director for the National Microelectronic Security Training Center (MEST). He also served as the Associate Chair for Research and Strategic Initiatives for the ECE Department from 2017-2019 and the Program Director of Cybersecurity in the Herbert Wertheim College of Engineering from 2019-2022. His current research projects include: hardware security and trust, electronics supply chain security, IoT security, and reliable and testable VLSI design. Dr. Tehranipoor has published numerous journal articles and refereed conference papers and has delivered more than 220+ invited talks and keynote addresses. In addition, he has 15 patents issued, and has published 13 books of which two are textbooks. His projects have been sponsored by 50+ companies and Government agencies.

Dr. Tehranipoor is a Fellow of IEEE, Fellow of ACM, Golden Core Member of IEEE Computer Society, and Member of ACM SIGDA. He is also a member of the Connecticut Academy of Science and Engineering (CASE). He is a recipient of 14 best paper awards and nominations, the 2009 NSF CAREER award, the 2014 AFOSR MURI award on Nanoscale Security, the 2008 IEEE Computer Society (CS) Meritorious Service award, the 2012 and 2017 IEEE CS Outstanding Contribution, the 2010 and 2016 IEEE TTTC/CS Most Successful Technical Event for co-founding and chairing HOST Symposium, the 2018 IEEE HOST Hall of Fame Member, the 2009 and 2014 UConn ECE Research Excellence award, the 2012 UConn SOE Outstanding Faculty Advisor award, the 2016 UF College of Engineering Excellence in Leadership award, the 2016 UF ECE Research Excellence Award, the 2020 UF’s College of Engineering Teacher/Scholar of the year award, and the 2020 UF Innovation of the Year Award.

He serves on the program committee of more than a dozen leading conferences and workshops. Prof. Tehranipoor served as the guest editor for JETTA, IEEE Design and Test of Computers, ACM JETC, and IEEE Computer Society Computing Now. He served as Program Chair of the 2019 International Test Conference (ITC), Vice-program Chair of the 2018 ITC, Program Chair of the 2007 IEEE Defect-Based Testing (DBT) workshop, 2016 IEEE International Verification and Security Workshop (IVSW), Program Chair of the 2008 IEEE Defect and Data Driven Testing (D3T) workshop, Co-program Chair of the 2008 International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), General Chair for D3T-2009 and DFTS-2009, and Vice-general Chair for NATW-2011, General Chair for 2008-2009, and 2021 IEEE HOST, and General Chair for 2019-2021 IEEE PAINE Conference.

Over the years, he has led a number of major initiatives in the domain of microelectronics security and trust. He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) and served as HOST-2008 and HOST-2009 General Chair and continue to serve as Chair of the Steering Committee for HOST. He also co-founded IEEE Asian-HOST and the IEEE International Conference of Physical Assurance and Inspection of Electronics (PAINE). Further, he co-founded the Journal on Hardware and Systems Security (HaSS) and currently serving as EIC for HaSS. He is also led development of Trust-Hub sponsored by the National Science Foundation (NSF). He served as associate Editor-in-Chief (EIC) for IEEE Design and Test of Computers from 2012-2014. He is currently serving as an Associate Editor for IEEE Design and Test of Computers, JETTA, Journal of Low Power Electronics (JOLPE), ACM Transactions for Design Automation of Electronic Systems (TODAES), IEEE Transactions on Computers, and IEEE Transactions on VLSI (TVLSI). He has served as an IEEE Distinguished Speaker and an ACM Distinguished Speaker from 2010-2013. Further, he served as an ambassador of cybersecurity for IEEE from 2016-2020.

Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut.

Navid Asadi is an Associate Professor in the Electrical and Computer Engineering Department at the University of Florida with an affiliation to the Materials Science and Engineering department. He investigates novel techniques for electronics inspection and assurance, system and chip level decomposition and security assessment, anti-reverse engineering, 3D imaging, invasive and semi-invasive methods, supply chain security, etc. Dr. Asadi is director of the Security and Assurance (SCAN) lab house to more than $12M advanced imaging and characterization equipment. He also serves as the associate director of the Florida Semiconductor Institute (FSI), and the Microelectronics Security Training (MEST) center which is a multi-million dollar program to train and reskill the professional engineers in the area of security. Dr. Asadi  has received his NSF CAREER award in 2022 and several best paper awards from IEEE International Symposium on Hardware Oriented Security and Trust (HOST) and the ASME International Symposium on Flexible Automation (ISFA). He was also winner of D.E. Crow Innovation award from University of Connecticut. He is also the general chair of the IEEE Physical Assurance and Inspection of Electronics (PAINE) Conference. His projects are sponsored by various government agencies and industry including but not limited to NSF, AFRL, AFOSR, ONR, SRC, Meta, Cisco, Analog Devices, etc.