IP Protection using Logic Locking

Instructor 

Dr. Ujjwal Guin is a Godbold Associate Professor in the Department of Electrical and Computer Engineering at Auburn University.

Learning Objectives

The IP Protection using Logic Locking micro-certificate course introduces students to state-of-the-art hardware design-for-security (DFS) techniques used to protect intellectual property (IP) in integrated circuit (IC) design and fabrication. With the globalization of semiconductor manufacturing and the increased risk of hardware piracy, overproduction, and reverse engineering, logic locking has emerged as a key solution for securing design assets. This course covers both the theoretical and practical aspects of logic locking—starting from foundational locking schemes and Boolean satisfiability (SAT) analysis to practical implementation and assessment techniques using logic insertion and optical probing. Learners will gain exposure to key gate-based obfuscation techniques, SAT-based attacks and countermeasures, and real-world probing strategies that expose vulnerabilities in logic-locked circuits. By the end of this course, participants will develop a comprehensive understanding of how to implement, test, and evaluate logic locking schemes to ensure strong IP protection in modern SoC and ASIC designs.

In this certificate course, students will learn the fundamentals and advanced methods of protecting hardware IP through logic locking—a security technique used to prevent piracy, reverse engineering, and unauthorized overproduction of integrated circuits. This micro-certificate course is organized into the following units:

• Unit 1: Logic Locking Fundamentals and SAT-based Analysis: Students will explore foundational locking mechanisms such as Random Logic Locking (RLL), Strong Logic Locking (SLL), and SAT-based attacks on locked circuits. The unit introduces Boolean Satisfiability (SAT) Analysis for fault detection and discusses practical locking insertion and assessment techniques using industry-grade tools like Synopsys Design Compiler, TetraMAX, and Yosys.
• Unit 2: Optical Probing Assessment on Logic Locking: This unit introduces optical probing techniques such as photon emission microscopy and laser fault analysis for detecting vulnerabilities in logic-locked designs. Students will gain practical insights into backside analysis, microscope instrumentation (PHEMOS 1000), and the interplay between physical fault injection and logic-level IP protection.
• Unit 3: Supplementary Lecture: Thinking of Logic Locking? Be Aware of the Existing Attacks!

Learning Outcomes:

• Explain the principles of logic locking and its role in IP protection.
• Implement basic and advanced logic locking techniques in RTL or gate-level designs.
• Understand and apply SAT-based attacks and countermeasures.
• Analyze locked designs using EDA tools and evaluate their resilience.
• Apply optical probing concepts to assess vulnerabilities in logic-locked hardware.
• Develop awareness of practical challenges in securing ICs across the design and fabrication lifecycle.

Prerequisites:

• Basic understanding of digital logic design and hardware security principles.
• Prior knowledge of Verilog RTL design, SAT-based testing, or semiconductor manufacturing workflows.
• Recommended: Familiarity with EDA tools such as Synopsys Design Compiler, TetraMAX, or MiniSAT.
• Recommended: MEST Micro-Certificate: Boolean Satisfiability Attack and Its Use in VLSI Testing

Biography

Ujjwal Guin is a Godbold Associate Professor in the Department of Electrical and Computer Engineering at Auburn University. He received his Ph.D. from the University of Connecticut in 2016. He is actively engaged in research projects spanning hardware security and trust, supply chain security, cybersecurity, and VLSI design and testing. He has developed several on-chip structures and techniques to enhance the security, trustworthiness, and reliability of integrated circuits. His contributions include authoring one book, two book chapters, thirty journal articles, and more than forty refereed conference papers. His research has been widely recognized through best paper nominations, awards, research grants, and prizes from various security competitions. Notably, one of his papers was referenced in the White House 100-Day Reviews under the EO 14017 report, specifically in the “Building Resilient Supply Chains” section, published in June 2021. Dr. Guin’s research projects are funded by the U.S. Army, the Air Force Office of Scientific Research (AFOSR), the Secret Service, the National Science Foundation (NSF), and the Air Force Research Laboratory (AFRL). He served on the technical program committees of several prestigious conferences, including DAC, ITC, HOST, VTS, PAINE, VLSID, GLSVLSI, ISVLSI, and Blockchain. He is currently the Technical Program Co-Chair of HOST 2025. He is a Senior Member of IEEE and ACM.

Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity and the Chair of the Department of Electrical and Computer Engineering (ECE) at the University of Florida. He is also currently serving as the Director for Florida Institute for Cybersecurity (FICS) Research, Director for Edaptive Computing Inc. Transition Center (ECI-TC), Co-director for the AFOSR/AFRL Center of Excellence on Enabling Cyber Defense in Analog and Mixed Signal Domain (CYAN), and Co-Director for the National Microelectronic Security Training Center (MEST). He also served as the Associate Chair for Research and Strategic Initiatives for the ECE Department from 2017-2019 and the Program Director of Cybersecurity in the Herbert Wertheim College of Engineering from 2019-2022. His current research projects include: hardware security and trust, electronics supply chain security, IoT security, and reliable and testable VLSI design. Dr. Tehranipoor has published numerous journal articles and refereed conference papers and has delivered more than 220+ invited talks and keynote addresses. In addition, he has 15 patents issued, and has published 13 books of which two are textbooks. His projects have been sponsored by 50+ companies and Government agencies.

Dr. Tehranipoor is a Fellow of IEEE, Fellow of ACM, Golden Core Member of IEEE Computer Society, and Member of ACM SIGDA. He is also a member of the Connecticut Academy of Science and Engineering (CASE). He is a recipient of 14 best paper awards and nominations, the 2009 NSF CAREER award, the 2014 AFOSR MURI award on Nanoscale Security, the 2008 IEEE Computer Society (CS) Meritorious Service award, the 2012 and 2017 IEEE CS Outstanding Contribution, the 2010 and 2016 IEEE TTTC/CS Most Successful Technical Event for co-founding and chairing HOST Symposium, the 2018 IEEE HOST Hall of Fame Member, the 2009 and 2014 UConn ECE Research Excellence award, the 2012 UConn SOE Outstanding Faculty Advisor award, the 2016 UF College of Engineering Excellence in Leadership award, the 2016 UF ECE Research Excellence Award, the 2020 UF’s College of Engineering Teacher/Scholar of the year award, and the 2020 UF Innovation of the Year Award.

He serves on the program committee of more than a dozen leading conferences and workshops. Prof. Tehranipoor served as the guest editor for JETTA, IEEE Design and Test of Computers, ACM JETC, and IEEE Computer Society Computing Now. He served as Program Chair of the 2019 International Test Conference (ITC), Vice-program Chair of the 2018 ITC, Program Chair of the 2007 IEEE Defect-Based Testing (DBT) workshop, 2016 IEEE International Verification and Security Workshop (IVSW), Program Chair of the 2008 IEEE Defect and Data Driven Testing (D3T) workshop, Co-program Chair of the 2008 International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), General Chair for D3T-2009 and DFTS-2009, and Vice-general Chair for NATW-2011, General Chair for 2008-2009, and 2021 IEEE HOST, and General Chair for 2019-2021 IEEE PAINE Conference.

Over the years, he has led a number of major initiatives in the domain of microelectronics security and trust. He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) and served as HOST-2008 and HOST-2009 General Chair and continue to serve as Chair of the Steering Committee for HOST. He also co-founded IEEE Asian-HOST and the IEEE International Conference of Physical Assurance and Inspection of Electronics (PAINE). Further, he co-founded the Journal on Hardware and Systems Security (HaSS) and currently serving as EIC for HaSS. He is also led development of Trust-Hub sponsored by the National Science Foundation (NSF). He served as associate Editor-in-Chief (EIC) for IEEE Design and Test of Computers from 2012-2014. He is currently serving as an Associate Editor for IEEE Design and Test of Computers, JETTA, Journal of Low Power Electronics (JOLPE), ACM Transactions for Design Automation of Electronic Systems (TODAES), IEEE Transactions on Computers, and IEEE Transactions on VLSI (TVLSI). He has served as an IEEE Distinguished Speaker and an ACM Distinguished Speaker from 2010-2013. Further, he served as an ambassador of cybersecurity for IEEE from 2016-2020.

Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut.