LLM based SoC Security verification I

Instructor 

Dr. Farimah Farahmandi is the Wally Rhines Endowed Professor in Hardware Security in the Department of Electrical and Computer Engineering (ECE) at the University of Florida

Learning Objectives

In this course, students learn how Large Language Models (LLMs) can be used to perform key SoC security verification tasks—security question-answering, security asset identification, and automated property/SVA generation. Through hands-on modules, students explore Retrieval-Augmented Generation (RAG), CWE-guided reasoning, RTL parsing, threat modeling, and assertion synthesis. By the end, students will understand how LLM-based workflows can strengthen pre-silicon hardware security verification.

The LLM-Based SoC Security Verification I micro-certificate introduces students to foundational AI-assisted hardware security workflows, focusing on how Large Language Models (LLMs) can support SoC verification tasks such as security question-answering, asset identification, and security property generation. With the growing complexity of modern SoCs and the expanding range of hardware vulnerabilities, traditional manual verification methods struggle to keep pace. LLMs offer a transformative approach—capable of interpreting natural-language specifications, parsing RTL, mapping vulnerabilities using CWE, and producing verification-ready SystemVerilog Assertions (SVAs).

This course covers three major LLM-driven verification pipelines:

• Unit 1: Security Question Answering through RAG:  explores Retrieval-Augmented Generation (RAG) for security question-answering, highlighting how curated knowledge bases help prevent hallucinations and improve accuracy in hardware-focused queries. Students learn how RAG systems retrieve CWE entries, research papers, and design guidelines to support accurate reasoning in SoC security tasks.
• Unit 2: Security Asset Identification using LLM: focuses on automated security asset identification using LLMs. Students study how conceptual and structural assets are discovered from specifications and RTL, how attackers target these design elements, and how asset classification (primary vs. secondary) connects to threat analysis and CWE mapping.
• Unit 3: Security Property & SystemVerilog Assertion Generation using LLM: demonstrates property generation using LLMs, where students see how natural-language security requirements can be converted into structured security properties and SystemVerilog Assertions. The methodology emphasizes Design-to-CWE mapping, Threat-vector analysis, and LLM self-reflection loops to ensure correctness and high-quality SVA output.

Learning Outcomes:

By the end of the course, students will understand how modern LLM pipelines enhance pre-silicon security verification and how these AI-driven methods integrate into a real SoC design environment. Students will be able to:

1. Explain the limitations of general LLMs in hardware security and the advantages of RAG-based architectures.
2. Use RAG pipelines to retrieve CWE entries and domain-specific documents to answer SoC security questions.
3. Identify conceptual and structural SoC security assets using LLM-driven RTL and specification analysis.
4. Apply the SA-EDI and IEEE P3164 principles for asset classification (primary/secondary, CIA-based).
5. Perform CWE-guided vulnerability mapping for identified assets.
6. Generate high-quality natural-language security properties using structured prompts and CWE context.
7. Produce and validate SystemVerilog Assertions aligned with SoC security needs.
8. Understand how LLM-driven verification workflows integrate into pre-silicon security verification environments.

Prerequisites:

• Basic understanding of RTL design, SoC architecture, and hardware security concepts
• Familiarity with SystemVerilog Assertions (SVA), CWE taxonomy, and threat modeling
• Prior exposure to LLM frameworks (RAG, fine-tuning, prompting) or EDA verification flows is desired but not required.
• MEST Micro-Certificate: Introduction to Large Language Models (LLMs) (reccommended)
• MEST Micro-certificate: System-on-Chip (SoC) Verification (reccommended)

Target Audience

Designed for professionals working in the Department of War / Government, government-affiliated employees, industry, as well as college students and faculty. Participants must register with their organizational email and will be notified of acceptance within one week of the course start date.

Biography

Dr. Farimah Farahmandi is the Wally Rhines Endowed Professor in Hardware Security in the Department of Electrical and Computer Engineering (ECE) at the University of Florida. She also serves as the Associate Director of the Florida Institute for Cybersecurity (FICS) at the University of Florida. Her research focuses on hardware security verification, formal methods, fault-injection attack analysis, and post-silicon validation and debug, resulting in 7 books and over 140 publications in these fields. Dr. Farahmandi’s research has been sponsored by a variety of leading companies and government agencies. For her contributions, she is a recipient of 7 best paper and nomination awards, and was recognized with the ACM/IEEE DAC Under 40 Innovators Award (2024), the Best Assistant Professor Award at the University of Florida (2024), the Excellence in Service Award (2023), and the Excellence in Research Award (2022) from the ECE department at UF. She also received the prestigious Young Faculty Award from SRC (2022) and the NSF CAREER Award.