LLM based SoC Security verification II

Instructor 

Dr. Farimah Farahmandi is the Wally Rhines Endowed Professor in Hardware Security in the Department of Electrical and Computer Engineering (ECE) at the University of Florida

Learning Objectives

In this course, students learn how Large Language Models (LLMs) can be applied to automate and enhance critical SoC security verification tasks, including threat modeling and security test plan creation, RTL testbench generation, and hardware security bug detection. Through hands-on modules, students work with Retrieval-Augmented Generation (RAG), RTL analysis, threat identification, test scenario synthesis, and vulnerability validation. By the end of the course, students gain a clear understanding of how LLM-driven workflows can improve the coverage, scalability, and effectiveness of pre-silicon hardware security verification.

The LLM Based SoC Security Verification II micro-certificate introduces students to advanced AI- and LLM-assisted techniques that build upon the foundations established in LLM Based SoC Security Verification I. This micro-certificate focuses on automating key hardware security verification tasks, including threat modeling and security test plan generation, LLM-driven synthesis of security-focused RTL testbenches, and systematic detection of RTL-level security bugs. Through hands-on, agentic workflows, learners gain practical experience in scalable, evidence-driven verification of modern SoC designs.

This course covers three major LLM-driven steps for hardware security verification:

• Unit 1: Threat Modeling and test Plan Generation using LLM: This lab training module teaches how to use Large Language Models in an agentic, retrieval-augmented framework to automate hardware security threat modeling and generate structured, design-aware security test plans. Participants learn to analyze physical, supply-chain, and software-exploitable threats by extracting security policies from hardware specifications and ISA documents, and translating them into actionable verification tasks using multi-agent reasoning and human-in-the-loop refinement.
• Unit 2: LLM based Testbench Generation for Bug Detection: This lab teaches how to use a multi-agent, LLM-driven framework to automatically generate security-focused RTL testbenches that detect and validate hardware vulnerabilities. Students learn how LLMs analyze RTL designs and CWE descriptions to form bug hypotheses, generate temporally precise test scenarios, and synthesize executable SystemVerilog testbenches that trigger real security flaws in simulation.
• Unit 3: Hardware Bug Detection with LLM: This lab module teaches how Large Language Models can be applied to automatically detect security-critical bugs in RTL finite state machine designs, reducing reliance on manual and rule-based verification. Participants learn to use the SecRT-LLM framework to analyze Verilog code and identify structural vulnerabilities such as Hamming distance violations, deadlocks, unreachable states, and duplicate state encodings through guided prompting and fidelity checking.

Learning Outcomes:

Across these three lab modules, learners are expected to achieve the following learning outcomes:

1. Explain how agentic LLM architectures overcome the limitations of manual and rule-based hardware security verification, particularly for threat modeling, RTL vulnerability detection, and test generation.
3. Use retrieval-augmented and in-context LLM pipelines to extract security policies, attack knowledge, and CWE-aligned vulnerability descriptions from hardware specifications, ISAs, and RTL designs.
4. Identify and classify hardware security threats across physical, supply-chain, architectural, and RTL-level attack surfaces using LLM-driven reasoning and user-guided context refinement.
5. Apply LLM-based analysis to detect structural RTL security bugs, including FSM deadlocks, unreachable states, Hamming distance violations, and duplicate state encodings.
6. Generate structured security verification artifacts using LLMs, including threat models, bug hypotheses, security policies, test objectives, and temporally aligned test scenarios.
7. Synthesize and execute security-focused verification collateral, such as SystemVerilog testbenches and simulation-based tests, to validate LLM-identified vulnerabilities with runtime evidence.
8. Evaluate the trustworthiness and limitations of LLM-generated security insights by correlating model explanations with simulation outcomes, fidelity checks, and known real-world hardware failure cases.

Prerequisites:

• Basic understanding of RTL design, SoC architecture, and hardware security concepts
• Familiarity with SystemVerilog testbench, threat modeling, and hardware level bugs
• Prior exposure to LLM frameworks (RAG, and prompting) or EDA verification flows is desired but not required.
• MEST Micro-Certificate: Introduction to Large Language Models (LLMs) (recommended)
• MEST Micro-certificate: LLM Based SoC Security Verification I (recommended)

Biography

Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity and the Chair of the Department of Electrical and Computer Engineering (ECE) at the University of Florida. He is also currently serving as the Director for Florida Institute for Cybersecurity (FICS) Research, Director for Edaptive Computing Inc. Transition Center (ECI-TC), Co-director for the AFOSR/AFRL Center of Excellence on Enabling Cyber Defense in Analog and Mixed Signal Domain (CYAN), and Co-Director for the National Microelectronic Security Training Center (MEST). He also served as the Associate Chair for Research and Strategic Initiatives for the ECE Department from 2017-2019 and the Program Director of Cybersecurity in the Herbert Wertheim College of Engineering from 2019-2022. His current research projects include: hardware security and trust, electronics supply chain security, IoT security, and reliable and testable VLSI design. Dr. Tehranipoor has published numerous journal articles and refereed conference papers and has delivered more than 220+ invited talks and keynote addresses. In addition, he has 15 patents issued, and has published 13 books of which two are textbooks. His projects have been sponsored by 50+ companies and Government agencies.

Dr. Tehranipoor is a Fellow of IEEE, Fellow of ACM, Golden Core Member of IEEE Computer Society, and Member of ACM SIGDA. He is also a member of the Connecticut Academy of Science and Engineering (CASE). He is a recipient of 14 best paper awards and nominations, the 2009 NSF CAREER award, the 2014 AFOSR MURI award on Nanoscale Security, the 2008 IEEE Computer Society (CS) Meritorious Service award, the 2012 and 2017 IEEE CS Outstanding Contribution, the 2010 and 2016 IEEE TTTC/CS Most Successful Technical Event for co-founding and chairing HOST Symposium, the 2018 IEEE HOST Hall of Fame Member, the 2009 and 2014 UConn ECE Research Excellence award, the 2012 UConn SOE Outstanding Faculty Advisor award, the 2016 UF College of Engineering Excellence in Leadership award, the 2016 UF ECE Research Excellence Award, the 2020 UF’s College of Engineering Teacher/Scholar of the year award, and the 2020 UF Innovation of the Year Award.

He serves on the program committee of more than a dozen leading conferences and workshops. Prof. Tehranipoor served as the guest editor for JETTA, IEEE Design and Test of Computers, ACM JETC, and IEEE Computer Society Computing Now. He served as Program Chair of the 2019 International Test Conference (ITC), Vice-program Chair of the 2018 ITC, Program Chair of the 2007 IEEE Defect-Based Testing (DBT) workshop, 2016 IEEE International Verification and Security Workshop (IVSW), Program Chair of the 2008 IEEE Defect and Data Driven Testing (D3T) workshop, Co-program Chair of the 2008 International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), General Chair for D3T-2009 and DFTS-2009, and Vice-general Chair for NATW-2011, General Chair for 2008-2009, and 2021 IEEE HOST, and General Chair for 2019-2021 IEEE PAINE Conference.

Over the years, he has led a number of major initiatives in the domain of microelectronics security and trust. He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) and served as HOST-2008 and HOST-2009 General Chair and continue to serve as Chair of the Steering Committee for HOST. He also co-founded IEEE Asian-HOST and the IEEE International Conference of Physical Assurance and Inspection of Electronics (PAINE). Further, he co-founded the Journal on Hardware and Systems Security (HaSS) and currently serving as EIC for HaSS. He is also led development of Trust-Hub sponsored by the National Science Foundation (NSF). He served as associate Editor-in-Chief (EIC) for IEEE Design and Test of Computers from 2012-2014. He is currently serving as an Associate Editor for IEEE Design and Test of Computers, JETTA, Journal of Low Power Electronics (JOLPE), ACM Transactions for Design Automation of Electronic Systems (TODAES), IEEE Transactions on Computers, and IEEE Transactions on VLSI (TVLSI). He has served as an IEEE Distinguished Speaker and an ACM Distinguished Speaker from 2010-2013. Further, he served as an ambassador of cybersecurity for IEEE from 2016-2020.

Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut.

Dr. Farimah Farahmandi is the Wally Rhines Endowed Professor in Hardware Security in the Department of Electrical and Computer Engineering (ECE) at the University of Florida. She also serves as the Associate Director of the Florida Institute for Cybersecurity (FICS) at the University of Florida. Her research focuses on hardware security verification, formal methods, fault-injection attack analysis, and post-silicon validation and debug, resulting in 7 books and over 140 publications in these fields. Dr. Farahmandi’s research has been sponsored by a variety of leading companies and government agencies. For her contributions, she is a recipient of 7 best paper and nomination awards, and was recognized with the ACM/IEEE DAC Under 40 Innovators Award (2024), the Best Assistant Professor Award at the University of Florida (2024), the Excellence in Service Award (2023), and the Excellence in Research Award (2022) from the ECE department at UF. She also received the prestigious Young Faculty Award from SRC (2022) and the NSF CAREER Award.