LLM for RTL Generation​

Instructor 

Dr. Mark Tehranipoor is the dean of the Herbert Wertheim College of Engineering, a UF Distinguished Professor, and the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity.

Learning Objectives

The LLM for RTL Generation micro-certificate introduces students to the use of Large Language Models (LLMs) across several key hardware-design activities: generating RTL from natural-language specifications, modifying existing RTL while preserving intended functionality, and reconstructing hardware specifications from existing RTL. Rather than treating an LLM as a stand-alone code generator, the course emphasizes engineering workflows in which model outputs are constrained by design information and evaluated using deterministic tools, simulation, testbenches, security requirements, and iterative feedback.

Modern hardware development involves repeated translation among design intent, specifications, RTL implementations, security requirements, and engineering changes. These translations can be time-consuming and error-prone. LLMs can accelerate them, but apparently correct machine-generated RTL or documentation cannot be trusted simply because it is syntactically fluent. The course therefore focuses not only on generation, but also on grounding, verification, measurement, repair, and critical review of LLM-generated hardware artifacts.

The micro-certificate is organized into the following three units:

• Unit 1: Specification-to-RTL Generation and Verification: This unit introduces an LLM-assisted workflow for generating synthesizable RTL directly from a natural-language hardware specification. Students learn how a written specification, fixed interface contract, RTL coding guidelines, and hardware-security CWE information can be combined into a structured prompt that constrains the model’s output. The module uses the aes_key_ctrl register/control block of an AES-128 CTR design as its working exampleA major focus of the unit is that generated RTL must be evaluated at three separate levels: syntactic correctness, functional correctness, and security correctness. A design may compile successfully and even pass functional tests while still containing security weaknesses. Students therefore learn to use a golden testbench, CWE-guided security requirements, interface constraints, and a bounded compile–simulate–repair loop rather than accepting an LLM-generated design at face value.Students also learn how assumptions made by the model can be explicitly recorded for review and how prompt structure can constrain the model’s freedom by fixing the interface, coding rules, security rules, and output format.
• Unit 2: LLM-Assisted RTL Design Modification and Security Patching: This unit moves from generating a new design to modifying an existing, already functional RTL implementation. Students learn why modification is often more challenging than generation: a patch must correctly implement the requested change while simultaneously preserving every behavior that was not supposed to change. Minimality, interface stability, and regression preservation therefore become explicit requirements.The unit introduces several classes of modification, including vulnerability patches, access-control hardening, monitor instrumentation, and specification-driven engineering changes. Students learn that some changes must preserve the module boundary, while monitor instrumentation may legitimately add new interface signals. Every modification is evaluated not only by whether the design still compiles, but by whether the existing regression suite continues to pass and whether directed attack tests demonstrate that the original vulnerability has actually been removed.A central concept is the verification gate. A modification is accepted only when the pre-existing regression tests still pass and the previously successful attack tests fail against the patched design. Additional interface and minimality checks help prevent unintended changes. This teaches students that a plausible-looking patch-or even one that reports an error correctly—is insufficient unless it actually prevents the prohibited behavior.
• Unit 3: RTL-to-Specification Generation and Quality Evaluation: This unit examines the reverse transformation: using an LLM to generate a design specification from existing RTL. Students learn how RTL itself can act as a hard source of ground truth and how deterministic extraction scripts can identify ports, parameters, registers, and structural information before the LLM begins writing. These extracted facts are incorporated into the prompt and subsequently reused to evaluate the generated specification.Students study common failure modes of LLM-generated specifications, including omissions, hallucinated elements, incorrect widths, and incorrect descriptions of signal behavior. They use a bounded self-check loop to return missing ports, parameters, or required sections to the LLM and request a corrected specification.The unit also introduces quantitative evaluation. Generated specifications are evaluated using deterministic measures such as coverage, section completeness, and hallucination suspects, along with an optional LLM-based judge. Students learn that perfect lexical coverage does not guarantee semantic correctness and that the RTL remains the ultimate ground truth when automated metrics disagree.

  Finally, students conduct a round-trip test in which the generated specification is used to regenerate RTL, which is then simulated against a golden testbench. This provides practical evidence about whether the specification contains enough information to reconstruct the observable behavior of the original design.

Learning Outcomes:

1. Construct structured prompts for RTL generation using specifications, fixed interfaces, coding guidelines, and hardware-security requirements.
2. Distinguish syntactic, functional, and security correctness when evaluating machine-generated RTL.
3. Use compile–simulate–repair workflows to iteratively improve LLM-generated RTL based on actual compiler and simulator feedback.
4. Apply CWE-guided security requirements when generating or reviewing security-critical RTL.
5. Use LLMs to implement controlled modifications to existing RTL, including security patches, access-control hardening, monitor instrumentation, and engineering changes.
6. Evaluate RTL modifications using regression and attack-oriented verification, ensuring that requested fixes work without breaking existing functionality.
7. Assess modification minimality and interface stability to determine whether an LLM-generated patch is suitable for engineering review.
8. Generate structured hardware specifications from RTL using deterministic design facts as grounding information.
9. Measure specification quality using coverage, completeness, and hallucination-related metrics and critically interpret LLM-based judge results.
10. Perform round-trip validation from RTL → specification → RTL and explain the strengths and limitations of testbench-based evidence.

Prerequisites:

• Basic understanding of digital logic and RTL design.
• Familiarity with Verilog/SystemVerilog.
• Basic understanding of hardware simulation and testbenches.
• Basic Python programming is helpful for running the automation scripts.
• Introductory familiarity with Large Language Models and prompt engineering is helpful but not required.
• Basic knowledge of hardware-security concepts and CWE terminology is recommended, particularly for the security-aware RTL generation and modification exercises.

Target Audience

Designed for U.S. citizens working in the Department of War, Government, or Government-affiliated employees, industry, as well as college students and faculty. Must register with your organizational email and will be notified of acceptance within one week of the course start date.

Biography

Mark M. Tehranipoor is the dean for the Herbert Wertheim College of Engineering, a UF Distinguished Professor and the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity. Prior to being named dean, he was the Sachio Semmoto Chair in the UF Department of Electrical & Computer Engineering.

An internationally recognized cyber/hardware security expert and accomplished academic leader, Tehranipoor has built a distinguished career advancing research innovation, forging strategic partnerships and creating opportunities through years of leadership and scholarly accomplishments at the University of Florida. Tehranipoor is a proven, long-time leader at the college. As founder of the Florida Semiconductor Institute, founding director of UF’s Florida Institute for Cybersecurity Research, and co-director for the National Microelectronic Security Training Center, he plays a pivotal role in shaping the nation’s secure electronics ecosystem.

He is also a fellow of the Institute of Electrical and Electronics Engineers, the National Academy of Inventors, the Association for Computing Machinery, the International Academy of Artificial Intelligence Sciences, the International Artificial Intelligence Industry Alliance, and the Academy of Science, Engineering and Medicine of Florida. Tehranipoor has published 700 journal articles and refereed conference papers, and has delivered more than 250 invited talks and keynote addresses. In addition, he has 26 patents issued, 27 pending invention disclosures and has published 20 books, of which two are textbooks. His projects have been sponsored by more than 60 companies and government agencies.