Objective: The learning objective of this module is for trainees to gain hand experiences on the power analysis attack. Trainees will learn how to extra secret keys from AES crypto hardware block using side channel power analysis on FPGA step by step. (i) Monitoring devices to measure power traces from secure/unprotected AES modules, and (ii) scripts of DPA, CPA attacks to detect vulnerabilities on collected traces. (iii) Trainees will use the provided scripts on these traces to assess the amount of information leakage using TVLA test (i.e., An attacker exploits the correlation between the power consumed by the device and the data generated during computation). We demonstrate how to perform a correlation power analysis attack on an AES block implemented on a FPGA, using the ChipWhisperer CW305 FPGA target board.
Target Audience: Government officers, Scientists
Prerequisite Knowledge and Skills:
- programming knowledge: Verilog HDL, python, MATLAB
- A FPGA board experience
- basic knowledge of statistics
- familiarity with every-day cryptography, such as AES, PKC etc.
Resources Provided at the Training | Deliverables:
- Detailed description of set-ups used in training
- A video demo of the module
- Verilog, python and MATLAB scripts examples for analysis
Learning Outcome: This work has been done with the ChipWhisperer system. This setup can be used for a variety of other targets, including implementation of other hardware cores (ECC, SHA, etc.). By end of this course trainees will understand the how to power analysis attacks work in theory, and then how to extract secret keys from FPGA implementation of an AES core using the power analysis.