Objective: Side channel information via power and electromagnetic (EM) emanation has enabled adversarial attacks on cryptographic hardware modules, mostly targeting for extracting the secure key. EM side-channel assessment of various cryptographic designs enables us to evaluate underlying the side-channel vulnerabilities of a given IP both in pre-silicon and post-silicon stages. In this module, the trainees will learn different assessment aspects of EM side-channel based on FPGA design and physical EM traces.
Target Audience: Government officers, Scientists
Prerequisite Knowledge and Skills:
- programming knowledge: Verilog HDL
- Xilinx Vivado softwares
- A FPGA board experience
Resources Provided at the Training | Deliverables:
- Detailed description of set-ups used in training
- A video demo of the module
- Verilog and python scripts examples for analysis
Learning Outcome: By end of this course trainees will understand the how EM side analysis attacks work in theory, and then how to extract secret keys from FPGA implementation of an AES core using the power analysis.