Objective: A combating die and IC recycling (CDIR) sensor is a circuit that exploits the aging behavior due to manufacturing variations and in-field stresses such as NBTI and HCI. A ring-oscillator (RO)-based CDIR sensor can be used as a lifecycle odometer for electronic devices to identify the aging, hence, usage, of the electronic device and can provide detectability of a recycled (counterfeit) chip. This module provides a basic understanding of RO-based Chip Odometer design techniques in FPGAs, sources of error in odometer responses and aging modeling, and calculation of common security properties from odometer measurements. In this module, the trainees will detect the age of the chip (recycled/relabeled) based on chip odometer testing.
Target Audience: Government officers, Scientists
Prerequisite Knowledge and Skills:
- programming knowledge: Verilog HDL, python
- Xilinx Vivado softwares
- A FPGA board experience
Resources Provided at the Training | Deliverables:
- Detailed description of set-ups used in training
- A video demo of the module
- Verilog scripts examples for analysis
Learning Outcome: By end of this course trainees will understand the how N-CDIR works in theory. The reference ROs in these CDIRs remain quiet during the normal operation of the IC while the stressed RO gets aged at an accelerated pace utilizing NBTI of pMOS transistors. This helps to get a reasonable frequency difference between the reference and stressed ROs even though an IC is used only a very short duration. The trainees will learn how to generate an N-CDIR odometer on FPGA and observe the frequency difference of the stressed and reference RO pair and thus detect a counterfeit IC.