Objective: A Hardware Trojan is a malicious addition or modification of an integrated circuit (IC) which could be inserted at arbitrary stages in the development cycle to compromise the security of entire system. The learning objective of this module is for trainees to gain hand experiences on the hardware Trojan insertion and detection techniques. Trainees will learn how a typical hardware Trojan-infected AES (advanced encryption standard) cryptographic implementation is implemented at RTL (register-transfer level) and triggered through bitstream tampering on an FPGA platform. Also, trainees will also learn how to detect the malicious functionality with security property verification. This draft demonstrates how to insert and detect malicious logics on an FPGA device and Cadence Jaspergold software, respectively.
Target Audience: Government officers, Scientists
Prerequisite Knowledge and Skills:
- programming knowledge: Verilog HDL
- Cadence Jaspergold, Xilinx Vivado softwares and FPGA board experience
- basic knowledge of AES cipher
Resources Provided at the Training | Deliverables:
- Detailed description of set-ups used in training
- A video demo of the module
- Verilog, python scripts examples for analysis
Learning Outcome: By end of this lab trainees will learn about a typical information leakage type hardware Trojan, FPGA development procedure, and bitstream tampering. Also, they are expected to learn about how to use security verification techniques for hardware Trojan detection with Cadence Jaspergold.