Objective: Logic Locking is one of the most widely popular ways of protecting an IP from untrusted foundry and end-users. A protective circuitry can be added at different abstractions of a design (i.e., high-level, rtl, or gate-level) to ensure the design only works when a correct set of keys is applied. The performance of the locking depends on the corruptibility added due to applying wrong keys and resilience to different well-known attacks. Then, trainees will perform the SAT attack on combinational logic locking-extraction of the correct key from a locked design. Then, validate it with the correct key by simulation and compare with the key that was used to lock the design.
Target Audience: Government officers, Scientists
Prerequisite Knowledge and Skills:
- programming knowledge: Verilog HDL
- Xilinx Vivado softwares
- basic knowledge of AES and RSA
Resources Provided at the Training | Deliverables:
- Detailed description of set-ups used in training
- A video demo of the module
Learning Outcome: By the end of this course and experiment, trainees will learn how to perform the SAT attack on combinational logic locking-extraction of the correct key from a locked design.