Objective: The flow for an Soc generation typically follows steps such as RTL preparation, modular and flattened synthesis (gate-level), formal equivalence, scan insertion and test pattern generation, parasitic extractions and sign-offs, and layout generation. In this module, trainees will learn the end-to-end process of designing a system-on-chip in the pre-silicon phase. This will provide an in-depth knowledge on IP selection, modification, integration and bus definition, and test and verification techniques. In the simulation domain, the trainees can get access to each of these steps and get accustomed with a typical design flow with the availability of necessary test and validation dataset.
Target Audience: Government officers, Scientists
Prerequisite Knowledge and Skills:
- programming knowledge: Verilog HDL
- Xilinx Vivado softwares
- Basic of SoC Architecture
Resources Provided at the Training | Deliverables:
- Detailed description of set-ups used in training
- A video demo of the module
- Verilog scripts examples for analysis
Learning Outcome: In this module, trainees will learn an in-depth knowledge on IP selection, modification, integration and bus definition, and test and verification techniques. In the simulation domain, the trainees can get access to each of these steps and get accustomed with a typical design flow with the availability of necessary test and validation dataset.