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Security Primitives I: Introduction to Physical Unclonable Functions

May 27, 2025 by Limor Herb

Date/Time
Date(s) - 05/27/2025 - 05/31/2030
12:00 AM
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Instructor 

Dr. Jim Plusquellic is a professor in the Electrical and Computer Engineering Department at the University of New Mexico and President and CEO, IC-Safety.

Learning Objectives

Physical Unclonable Functions (PUFs) are hardware security primitives that are capable of generating keying material for security functions such as encryption and authentication. PUFs are unique in that they can generate and regenerate keys on-the-fly without the need to store the keys to any type of non-volatile memory, e.g., flash, hard-drive, etc. The keys are generated by measuring small performance differences that exist from one copy of a device to another, i.e., every iPhone 15 that is manufactured is slightly different than all other iPhone 15 in the population. The small random performance differences that exist among devices are referred to as entropy. The PUF on a device measures these small random performance differences and creates a digital string of 1’s and 0’s, i.e., a bitstring. Given that the performance differences are random, each device possesses a unique digital string that can be used as a key for encryption operations or as a unique identifier for authentication. This course describes PUF architectures and the statistical evaluation methods that can be used to evaluate the quality of the PUF-generated bitstrings.

Students taking this course will learn about the benefits, limitations, statistical characterization techniques and architectural features of physical unclonable functions (PUFs) The focus of the instruction is on microelectronic implementations of PUFs in standard CMOS process technologies.

This micro-certificate course is organized into a set of Units, described as follows:

  • Unit 1: Introduction on PUFs: Definition of a PUF, and a discussion on the source of entropy (randomness) that PUFs leverage.
  • Unit 2: Statistics: Instruction on the standard statistical techniques that have emerged to evaluate the quality of the PUF.
  • Unit 3: Classes and Applications: Contains a discussion on the different classes that can be used to characterize PUF architectures, followed with instruction on important security applications that are relevant to PUFs.
  • Unit 4: Supplemental Lectures: A presentation on the types of embedded instrumentation that are useful for PUF architectures is provided. In particular, PUFs that leverage resistance and delay variations as a source of entropy can utilize a voltage-to-digital converter (VDC) and a time-to-digital converter (TDC) to improve statistical metrics, including the uniqueness and reliability of the PUF.

Prerequisites:

  • A background in Very Large Scale Integration (VLSI) and Field Programmable Gate Arrays (FPGAs) is desirable but not required.

Biography

Professor Plusquellic received his M.S. and Ph.D. degrees in Computer Science from the University of Pittsburgh in 1995 and 1997, respectively. He is currently a professor of electrical and computer engineering at the University of New Mexico. His research interests are in the area of nano-scale VLSI and include security and trust in IC hardware, embedded system design, supply chain and IoT security and trust, silicon validation, design for manufacturability, and delay test methods. Professor Plusquellic received an “Outstanding Contribution Award” from the IEEE Computer Society in 2012 for co-founding and his contributions to the Symposium on Hardware-Oriented Security and Trust (HOST), and again recently in 2017 for “Co-Founder of and providing Outstanding Contributions to the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) for the Past Ten Years 2008-2017”. He is the Trust and Assurance Lead for ASU’s ME COMMONS (SWAP) Hub since July 2024. He served as General Chair for HOST in 2010, as Program Chair for HOST in 2008, 2009, and 2020, and as panelist and moderator for panels at HOST 2020. He has served as Associate Editor for Transactions on Computers and is
currently serving as Editor-in-Chief of Hardware Security for Cryptography, MDPI. He has recently been inducted into the HOST Hall-of-Fame and has authored or co-authored three book chapters for Springer Link on the topics of PUF-based Authentication and Hardware Trojan Detection. He received the “10 Years of Continuous Service Award” from the International Test Conference, a Best Paper Award from VTS, an ACM Distinguished Service Award from SIGDA, and two Austin CAS Fellow Awards from IBM. He received the “Albuquerque lab-to-business accelerator” award in 2016, the “2014 Innovation Award” from the Science and Technology Center at the University of New Mexico, was a “Featured Entrepreneur” within the School of Engineering, and has multiple patents and provisional applications filed with the US. Patent and Trademark Office. Professor Plusquellic is President and CEO of IC-Safety, LLC, and a consultant for Enthentica Inc., both start-ups in the hardware security and trust space. He has published more than 140 refereed conference and journal papers. He is a Golden Core Member of the IEEE Computer Society.



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