Security Primitives II: PUF Architectures

Instructor 

Dr. Jim Plusquellic is a professor in the Electrical and Computer Engineering Department at the University of New Mexico and President and CEO, IC-Safety.

Learning Objectives

Physical Unclonable Functions (PUFs) leverage small differences in the behavior of identically designed devices to generate device-specific keys, bitstrings and random numbers. A PUF architecture defines a source of entropy and an algorithm that measures and processes random variations which occur in the entropy source into a digital sequence of 0’s and 1’s. In this course, we will investigate several PUF architectures, and discuss the impact of adverse environmental conditions on the statistical quality and reliability of the generated bitstrings. A set of laboratory exercises is included to give trainees experience with designing PUFs on field programmable gate arrays.

PUFs are designed to measure and digitize electrical signal variations that occur in the device that occur because of the non-zero tolerance associated with the manufacturing process. These variations introduce small differences in identically designed devices, i.e., the delay along paths implemented with logic gates is different in each copy of the device. An important goal when designing a PUF is to select a circuit parameter that exhibits random behavior across devices, and to avoid circuit parameters that possess systematic bias. Systematic bias adversely impacts the statistical quality of the PUF-generated bitstrings because different copies of the device can produce similar bitstrings. We investigate several PUF architectures in this course, that incrementally improve on the ability of the PUF to produce high quality bitstrings. Three PUF architectures are discussed including:

• Unit 1: Ring Oscillator (RO) PUF: An identically designed circuit structure that leverages delay variations as a source of entropy. The RO PUF is constructed as a localized circuit structure which creates a cyclic ring of gates which propagates a signal which behaves like a clock signal but whose frequency of oscillation is dependent on random variations that occur within the inverter gates defining the ring.
• Unit 2: Shift-Register (SR) PUF: A hybrid architecture that includes some elements that are identically designed and others that are not identically designed. Similar to the RO PUF, the SR PUF propagates a signal around a loop, and variations in the frequency of oscillation defines the source of entropy.
• Unit 3: Shift-Register, Reconvergent-Fanout (SiRF) PUF: A non-identically designed test structure that leverages variations that occur in path delays through an engineering netlist of logic gates. Unlike the RO and SR PUF, the delay variations are measured using a time-to-digital converter, and a sequence of post-processing operations are used to improve the statistical quality of the bitstrings.
• Unit 4: RO PUF laboratory: A set of two modules that walk trainees through the process of designing a ring oscillator PUF on an FPGA.
• Unit 5: Supplemental Material: A presentation on the types of embedded instrumentation that are useful for PUF architectures is also provided. In particular, PUFs that leverage resistance and delay variations as a source of entropy can utilize a voltage-to-digital converter (VDC) and a time-to-digital converter (TDC) to improve statistical metrics including the uniqueness and reliability of the PUF.

Prerequisites:

• A background in Very Large Scale Integration (VLSI) and Field Programmable Gate Arrays (FPGAs) is desirable but not required.
• MEST Security Primitives I: Introduction to Physically Unclonable Functions

Biography

Professor Plusquellic received his M.S. and Ph.D. degrees in Computer Science from the University of Pittsburgh in 1995 and 1997, respectively. He is currently a professor of electrical and computer engineering at the University of New Mexico. His research interests are in the area of nano-scale VLSI and include security and trust in IC hardware, embedded system design, supply chain and IoT security and trust, silicon validation, design for manufacturability, and delay test methods. Professor Plusquellic received an “Outstanding Contribution Award” from the IEEE Computer Society in 2012 for co-founding and his contributions to the Symposium on Hardware-Oriented Security and Trust (HOST), and again recently in 2017 for “Co-Founder of and providing Outstanding Contributions to the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) for the Past Ten Years 2008-2017”. He is the Trust and Assurance Lead for ASU’s ME COMMONS (SWAP) Hub since July 2024. He served as General Chair for HOST in 2010, as Program Chair for HOST in 2008, 2009, and 2020, and as panelist and moderator for panels at HOST 2020. He has served as Associate Editor for Transactions on Computers and is
currently serving as Editor-in-Chief of Hardware Security for Cryptography, MDPI. He has recently been inducted into the HOST Hall-of-Fame and has authored or co-authored three book chapters for Springer Link on the topics of PUF-based Authentication and Hardware Trojan Detection. He received the “10 Years of Continuous Service Award” from the International Test Conference, a Best Paper Award from VTS, an ACM Distinguished Service Award from SIGDA, and two Austin CAS Fellow Awards from IBM. He received the “Albuquerque lab-to-business accelerator” award in 2016, the “2014 Innovation Award” from the Science and Technology Center at the University of New Mexico, was a “Featured Entrepreneur” within the School of Engineering, and has multiple patents and provisional applications filed with the US. Patent and Trademark Office. Professor Plusquellic is President and CEO of IC-Safety, LLC, and a consultant for Enthentica Inc., both start-ups in the hardware security and trust space. He has published more than 140 refereed conference and journal papers. He is a Golden Core Member of the IEEE Computer Society.