Security Primitives III: True Random Number Generators

Instructor 

Dr. Jim Plusquellic is a professor in the Electrical and Computer Engineering Department at the University of New Mexico and President and CEO, IC-Safety.

Learning Objectives

True Random Number Generators (TRNGs) are hardware security primitives that are capable of generating very long random number sequences for use in cryptographic applications including encryption, authentication, attestation, secure boot, etc. TRNGs leverage sources of dynamic entropy, in contrast with PUFs which leverage static entropy, including power supply noise, chaos, jitter noise associated with clocks and metastability. Stand-alone TRNG architectures need to be very light-weight, low power and capable of generating 10’s of millions of random bits per second. Given their close relationship between PUFs and TRNGs, unified architectures that reuse components for both functions are proposed as a solution for implementations on low power, embedded IoT-based applications.

Physical Unclonable Function ArchitecturesTRNGs generate random bit sequences that must pass stringent statistical quality tests, including tests that measure the level of randomness and uniqueness across devices, and they must maintain this high statistical quality independent of the environmental conditions. The modules in this course will cover example TRNG architectures that leverage a variety of different noise sources, with additional instruction on the benefits of a unified PUF-TRNG architecture and the statistical test suites that have emerged as standards for measuring the quality of the bit sequences. Students taking this course will learn about the benefits, limitations, statistical characterization techniques and architectural features of True Random Number Generators (TRNGs). The focus of the instruction is on microelectronic implementations of TRNGs in standard CMOS process technologies.

The course is organized as follows:

• Unit 1: True Random Number Generators (TRNG): Introduction to TRNGs: Definition of a TRNG and a discussion on the four basic types of entropy which are leveraged by different classes of TRNGs.
• Unit 2: Unified TRNG-PUF Architectures: Unified TRNG-PUF Architectures: Discussion on the similarities and differences between PUFs and TRNGs, and the benefits of a unified architecture that is able to reuse components of the architecture to reduce area overhead.
• Unit 3: Statistics: Instruction on TRNG statistical testing methods is provided that enable evaluation of the statistical quality of the TRNG bit sequence.

A webinar on the types of embedded instrumentation that are useful for PUF architectures is also provided. In particular, PUFs that leverage resistance and delay variations as a source of entropy can utilize a voltage-to-digital converter (VDC) and a time-to-digital converter (TDC) to improve statistical metrics including the uniqueness and reliability of the PUF.

Prerequisites:

• A background in Very Large Scale Integration (VLSI) and Field Programmable Gate Arrays (FPGAs) is desirable but not required.
• MEST Security Primitives I: Introduction to Physically Unclonable Functions
• MEST Security Primitives II: Physically Unclonable Function Architectures (recommended)

Biography

Professor Plusquellic received his M.S. and Ph.D. degrees in Computer Science from the University of Pittsburgh in 1995 and 1997, respectively. He is currently a professor of electrical and computer engineering at the University of New Mexico. His research interests are in the area of nano-scale VLSI and include security and trust in IC hardware, embedded system design, supply chain and IoT security and trust, silicon validation, design for manufacturability, and delay test methods. Professor Plusquellic received an “Outstanding Contribution Award” from the IEEE Computer Society in 2012 for co-founding and his contributions to the Symposium on Hardware-Oriented Security and Trust (HOST), and again recently in 2017 for “Co-Founder of and providing Outstanding Contributions to the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) for the Past Ten Years 2008-2017”. He is the Trust and Assurance Lead for ASU’s ME COMMONS (SWAP) Hub since July 2024. He served as General Chair for HOST in 2010, as Program Chair for HOST in 2008, 2009, and 2020, and as panelist and moderator for panels at HOST 2020. He has served as Associate Editor for Transactions on Computers and is
currently serving as Editor-in-Chief of Hardware Security for Cryptography, MDPI. He has recently been inducted into the HOST Hall-of-Fame and has authored or co-authored three book chapters for Springer Link on the topics of PUF-based Authentication and Hardware Trojan Detection. He received the “10 Years of Continuous Service Award” from the International Test Conference, a Best Paper Award from VTS, an ACM Distinguished Service Award from SIGDA, and two Austin CAS Fellow Awards from IBM. He received the “Albuquerque lab-to-business accelerator” award in 2016, the “2014 Innovation Award” from the Science and Technology Center at the University of New Mexico, was a “Featured Entrepreneur” within the School of Engineering, and has multiple patents and provisional applications filed with the US. Patent and Trademark Office. Professor Plusquellic is President and CEO of IC-Safety, LLC, and a consultant for Enthentica Inc., both start-ups in the hardware security and trust space. He has published more than 140 refereed conference and journal papers. He is a Golden Core Member of the IEEE Computer Society.