The State-of-the-Art in Advanced Packaging Technologies

Instructor 

Dr. Jim Plusquellic is a professor in the Electrical and Computer Engineering Department at the University of New Mexico and President and CEO, IC-Safety.

Learning Objectives

Advanced packaging is increasingly used to improve yield with known-good-die (chiplets), and to support heterogeneous integration and the decomposition of monolithic designs to chiplets optimized to technology nodes. As a replacement to expensive monolithic chip manufacturing, 2.5D and 3D advanced packaging technologies allow entire systems to be tightly integrated into a system-in-package (SiP) at lower costs and with higher yields. Advanced packaging is able to encapsulate and interconnect sets of heterogeneous components including CPUs, AI engines, FPGAs, RF and memories with redistribution layer (RDL) wiring geometries that mimic wiring layer geometries of chips manufactured in the 1990s. The first module of this course presents the history of packaging up to, but not including, the present day, and covers package types including Dual-In-Line packages, QuadFlatPack, PinGridArrays and BallGridArrays (BGA). The benefits and limitations of Through Hole and Surface Mount Technology (SMT) package types are discussed. The second module provides an overview of Advanced Packaging Technologies, including 2.5D and 3D, including the drivers for including chiplets in a system-in-package (SiP), as well as a taxonomy of package types that exist and are being proposed. The third module describes the threat landscape and countermeasures of microelectronic systems implemented in 2.5 and 3D advanced packages, at each of the stages, from design through in-field operation.

• Unit 1: History of Packages: The history of packaging up to, but not including, the present day.
• Unit 2: Advanced Packaging Technologies: Presents an overview of Advanced Packaging Technologies, including 2.5D and 3D.
• Unit 3: Trust and Assurance Issues in Advanced Packages: Presents the threat landscape and countermeasures of microelectronic systems implemented in 2.5 and 3D advanced packages.

This micro-certificate course is organized into a set of Units, described as follows:

• Unit 1: History of Packages: This unit presents the history of packaging up to, but not including, the present day, and covers package types including Dual-In-Line packages, QuadFlatPack, PinGridArrays and BallGridArrays (BGA). The benefits and limitations of Through Hole and Surface Mount Technology (SMT) package types are discussed. Given the close relationship between packaging and Printed Circuit Boards (PCBs), the PCB manufacturing process is also described. Modern PCB manufacturing processes including reflow are described as a means of learning what drives BGA and other types of surface mount technologies. The challenges associated with package and PCB manufacture and reliable attachment mechanisms are discussed, including the concept of Coefficient of Thermal Expansion (CTE), as well as the types of package and PCB testing methods used, including the JEDEC standardized testing techniques.
• Unit 2: Advanced Packaging Technologies: This unit presents an overview of Advanced Packaging Technologies, including 2.5D and 3D. The drivers for including chiplets in a system-in-package (SiP) are described, as well as the major companies in the microelectronics space along with a description of their advanced package technologies. The module presents a taxonomy of package types that exist and are being proposed. The evolution from PCB to advanced packages and platform on a package is described. An overview of an advanced package interconnect standard called UCIe is covered, including example implementations and topologies, as well as the UCIe protocol stack. Examples of advanced package flows and CAD tools are described. The complete process flow for an advanced packaging technology called fan-out, wafer-level packaging (FOWLP) is presented as an exemplar.
• Unit 3: Trust and Assurance in Advanced Packages:  The primary learning objective of this unit is for trainees to be learn about the threat landscape and countermeasures of microelectronic systems implemented in 2.5 and 3D advanced packages. The module covers the drivers for migrating to advanced packages, compares features of monolithic chips with advanced packages and printed circuit boards and then describes the threat landscape at each of the stages, from design through in-field operation, of the advanced package life cycle. Examples of threats including IP piracy, counterfeit chiplets, reverse engineering, Hardware Trojans, side-channel attacks, information leakage, fault injection and firmware modifications are covered as well as a set of countermeasures that detect and/or mitigate these threats. Although many of the attacks on monolithic chips also exist in advanced packages, the threat landscape is expanded because of the disaggregation of functions across multiple chiplets and multiple foundries. This module emphasizes the expanded attack space that has emerged for advanced packages.

Prerequisites:

• A background in VLSI Design is useful but not required.
• An undergraduate degree in Computer Engineering would also be useful but not required.

Target Audience

Designed for U.S. citizens working in the Department of War, Government, or Government-affiliated employees, industry, as well as college students and faculty. Must register with your organizational email, and will be notified of acceptance within one week of the course start date.

Biography

Professor Plusquellic received his M.S. and Ph.D. degrees in Computer Science from the University of Pittsburgh in 1995 and 1997, respectively. He is currently a professor of electrical and computer engineering at the University of New Mexico. His research interests are in the area of nano-scale VLSI and include security and trust in IC hardware, embedded system design, supply chain and IoT security and trust, silicon validation, design for manufacturability, and delay test methods. Professor Plusquellic received an “Outstanding Contribution Award” from the IEEE Computer Society in 2012 for co-founding and his contributions to the Symposium on Hardware-Oriented Security and Trust (HOST), and again recently in 2017 for “Co-Founder of and providing Outstanding Contributions to the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) for the Past Ten Years 2008-2017”. He is the Trust and Assurance Lead for ASU’s ME COMMONS (SWAP) Hub since July 2024. He served as General Chair for HOST in 2010, as Program Chair for HOST in 2008, 2009, and 2020, and as panelist and moderator for panels at HOST 2020. He has served as Associate Editor for Transactions on Computers and is
currently serving as Editor-in-Chief of Hardware Security for Cryptography, MDPI. He has recently been inducted into the HOST Hall-of-Fame and has authored or co-authored three book chapters for Springer Link on the topics of PUF-based Authentication and Hardware Trojan Detection. He received the “10 Years of Continuous Service Award” from the International Test Conference, a Best Paper Award from VTS, an ACM Distinguished Service Award from SIGDA, and two Austin CAS Fellow Awards from IBM. He received the “Albuquerque lab-to-business accelerator” award in 2016, the “2014 Innovation Award” from the Science and Technology Center at the University of New Mexico, was a “Featured Entrepreneur” within the School of Engineering, and has multiple patents and provisional applications filed with the US. Patent and Trademark Office. Professor Plusquellic is President and CEO of IC-Safety, LLC, and a consultant for Enthentica Inc., both start-ups in the hardware security and trust space. He has published more than 140 refereed conference and journal papers. He is a Golden Core Member of the IEEE Computer Society.