Supply Chain Security

Instructor 

Dr. Mark Tehranipoor is the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity and the Chair of the Department of Electrical and Computer Engineering (ECE) at the University of Florida.

Learning Objectives

The globalization of semiconductor design and manufacturing has made the hardware supply chain vulnerable to threats such as IP piracy, counterfeiting, reverse engineering, and unauthorized overproduction. Traditional passive protections like patents or encryption are insufficient when untrusted foundries or third parties can manipulate or copy integrated circuits. Logic locking, a leading Design-for-Security (DfS) technique, actively protects hardware by inserting key-dependent gates that conceal true functionality unless the correct secret key is applied. This certificate provides an introduction to logic locking, its insertion and assessment, and explores advanced schemes such as random and strong logic locking to defend against sophisticated attacks. Learners gain practical skills in applying, testing, and evaluating these methods, which are critical to ensuring trust in the hardware supply chain.

Students will learn the principles of hardware supply chain security, focusing on logic locking as a defense against IP piracy, counterfeiting, and untrusted foundries. They will explore how to insert locking gates, evaluate the strength of different schemes, perform SAT-based attack analysis, and understand how stronger locking mechanisms resist such attacks. Through hands-on exercises, learners gain experience with synthesis, test pattern generation, and security evaluation workflows.

This micro-certificate course is organized into a set of units described below:

• Unit 1: Logic Locking Insertion and Assessment

       Introduces the concept of logic locking and its role in securing ICs from piracy and overproduction. Students perform logic gate insertion, visualize locked circuits using Yosys, and           evaluate security with SAT attacks. Verification techniques are covered to ensure locked circuits preserve functionality under correct keys.

• Unit 2: Different Locking Schemes for Preventing IP Piracy

       Provides an overview of Random Logic Locking (RLL), Strong Logic Locking (SLL), and ATPG-based analysis. Students learn how key sensitization attacks reveal vulnerabilities, and           how stronger schemes enhance resistance by ensuring pairwise security. Practical exercises demonstrate test pattern generation for locked designs and exploration of SAT-                     resilient approaches.

Prerequisites:

• A background in RTL design and C++ programming will be helpful.

Target Audience

Designed for U.S. citizens working in the Department of War, Government, or Government-affiliated employees, industry, as well as college students and faculty. Must register with your organizational email, and will be notified of acceptance within one week of the course start date.

Biography

Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity and the Chair of the Department of Electrical and Computer Engineering (ECE) at the University of Florida. He is also currently serving as the Director for Florida Institute for Cybersecurity (FICS) Research, Director for Edaptive Computing Inc. Transition Center (ECI-TC), Co-director for the AFOSR/AFRL Center of Excellence on Enabling Cyber Defense in Analog and Mixed Signal Domain (CYAN), and Co-Director for the National Microelectronic Security Training Center (MEST). He also served as the Associate Chair for Research and Strategic Initiatives for the ECE Department from 2017-2019 and the Program Director of Cybersecurity in the Herbert Wertheim College of Engineering from 2019-2022. His current research projects include: hardware security and trust, electronics supply chain security, IoT security, and reliable and testable VLSI design. Dr. Tehranipoor has published numerous journal articles and refereed conference papers and has delivered more than 220+ invited talks and keynote addresses. In addition, he has 15 patents issued, and has published 13 books of which two are textbooks. His projects have been sponsored by 50+ companies and Government agencies.

Dr. Tehranipoor is a Fellow of IEEE, Fellow of ACM, Golden Core Member of IEEE Computer Society, and Member of ACM SIGDA. He is also a member of the Connecticut Academy of Science and Engineering (CASE). He is a recipient of 14 best paper awards and nominations, the 2009 NSF CAREER award, the 2014 AFOSR MURI award on Nanoscale Security, the 2008 IEEE Computer Society (CS) Meritorious Service award, the 2012 and 2017 IEEE CS Outstanding Contribution, the 2010 and 2016 IEEE TTTC/CS Most Successful Technical Event for co-founding and chairing HOST Symposium, the 2018 IEEE HOST Hall of Fame Member, the 2009 and 2014 UConn ECE Research Excellence award, the 2012 UConn SOE Outstanding Faculty Advisor award, the 2016 UF College of Engineering Excellence in Leadership award, the 2016 UF ECE Research Excellence Award, the 2020 UF’s College of Engineering Teacher/Scholar of the year award, and the 2020 UF Innovation of the Year Award.

He serves on the program committee of more than a dozen leading conferences and workshops. Prof. Tehranipoor served as the guest editor for JETTA, IEEE Design and Test of Computers, ACM JETC, and IEEE Computer Society Computing Now. He served as Program Chair of the 2019 International Test Conference (ITC), Vice-program Chair of the 2018 ITC, Program Chair of the 2007 IEEE Defect-Based Testing (DBT) workshop, 2016 IEEE International Verification and Security Workshop (IVSW), Program Chair of the 2008 IEEE Defect and Data Driven Testing (D3T) workshop, Co-program Chair of the 2008 International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), General Chair for D3T-2009 and DFTS-2009, and Vice-general Chair for NATW-2011, General Chair for 2008-2009, and 2021 IEEE HOST, and General Chair for 2019-2021 IEEE PAINE Conference.

Over the years, he has led a number of major initiatives in the domain of microelectronics security and trust. He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) and served as HOST-2008 and HOST-2009 General Chair and continue to serve as Chair of the Steering Committee for HOST. He also co-founded IEEE Asian-HOST and the IEEE International Conference of Physical Assurance and Inspection of Electronics (PAINE). Further, he co-founded the Journal on Hardware and Systems Security (HaSS) and currently serving as EIC for HaSS. He is also led development of Trust-Hub sponsored by the National Science Foundation (NSF). He served as associate Editor-in-Chief (EIC) for IEEE Design and Test of Computers from 2012-2014. He is currently serving as an Associate Editor for IEEE Design and Test of Computers, JETTA, Journal of Low Power Electronics (JOLPE), ACM Transactions for Design Automation of Electronic Systems (TODAES), IEEE Transactions on Computers, and IEEE Transactions on VLSI (TVLSI). He has served as an IEEE Distinguished Speaker and an ACM Distinguished Speaker from 2010-2013. Further, he served as an ambassador of cybersecurity for IEEE from 2016-2020.

Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut.