System-on-Chip (SoC) Verification

Instructor 

Dr. Farimah Farahmandi is the Wally Rhines Endowed Professor in Hardware Security in the Department of Electrical and Computer Engineering (ECE) at the University of Florida

Learning Objectives

Verification in hardware design ensures that the design behaves as intended before fabrication, minimizing costly post-silicon errors. It involves checking functionality, bug, and compliance with specifications. Property-based formal verification is a mathematical approach where properties, typically written in SystemVerilog Assertions (SVA), define expected behavior, and tools exhaustively prove or disprove these against the design. At the system level, verification uses methodologies like UVM (Universal Verification Methodology), a reusable, object-oriented framework in SystemVerilog for testbench generation, and SystemC, a C++-based modeling platform for high-level architectural simulation. These verification methods offer numerous benefits, including reduced design bugs, faster time-to-market, and improved reliability. Security verification specifically targets vulnerabilities, ensuring the design is protected against threats such as side-channel attacks, Trojans, or unauthorized access. This is critical in modern SoCs where third-party IP and complex interactions can introduce subtle security flaws. Together, these methods enable robust, secure, and functionally correct hardware designs. This course describes basics of verification, property based formal verification and an intro to system level verification using SystemC-UVM.

Students will learn the basic methods of verification, how to write properties for formal verification, how to use SystemC-UVM libraries for a specific design and recent research on security verification.

This micro-certificate course is organized into a set of units described below.

• Unit 1: Basics of Verification: Introduces formal verification, writing properties and provides hands-on experience on using formal verification tools.
• Unit 2: Property Based Security Verification: describes about how to write security properties and verify those for a crypto accelerator such as AES using cadence JasperGold tool.
• Unit 3: System Level Verification using SystemC-UVM: describe the benefits of SystemC-UVM in SoC verification, setting up environments, and verification steps of a real-world design.
• Unit 4: Research Series on Security Verification: It contains three lectures on cutting-edge recent research on hardware security bug detection, security verification using formal methods, and automating security property generation for formal verification.

Prerequisites:

• A background in RTL design and C++ programming will be helpful.
• MEST Micro-certificate: Introduction to System-on-Chip (SoC) Design (recommended)

Biography

Dr. Farimah Farahmandi is the Wally Rhines Endowed Professor in Hardware Security in the Department of Electrical and Computer Engineering (ECE) at the University of Florida. She also serves as the Associate Director of the Florida Institute for Cybersecurity (FICS) at the University of Florida. Her research focuses on hardware security verification, formal methods, fault-injection attack analysis, and post-silicon validation and debug, resulting in 7 books and over 140 publications in these fields. Dr. Farahmandi’s research has been sponsored by a variety of leading companies and government agencies. For her contributions, she is a recipient of 7 best paper and nomination awards, and was recognized with the ACM/IEEE DAC Under 40 Innovators Award (2024), the Best Assistant Professor Award at the University of Florida (2024), the Excellence in Service Award (2023), and the Excellence in Research Award (2022) from the ECE department at UF. She also received the prestigious Young Faculty Award from SRC (2022) and the NSF CAREER Award.