Webinar: Security, FPGAs, and the Cloud: Fundamentals of FPGA-Accelerated Cloud Security

To watch the recorded webinar, click on the recording.

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Speaker: 

Dr. Jakub Szefer, Associate Professor of Electrical Engineering at Yale University

Abstract: 

The talk will cover recent research on thermal channels that can be used to create covert channels between users renting same FPGA over time, FPGA fingerprinting and reverse-engineering FPGA-enabled data center infrastructures, and voltage-based channels can be used to leak sensitive information across FPGAs (in single-tenant or multi-tenant settings), or can be combined with other existing attacks to perform cross-talk leakage inside the FPGAs (in multi-tenant settings).

Speaker Bio:

Dr. Jakub Szefer’s research focuses on computer architecture and hardware security. His research encompasses secure processor architectures, cloud security, FPGA attacks and defenses, and hardware FPGA implementation of cryptographic algorithms. His research is supported through National Science Foundation and industry grants and donations. He is currently an Associate Professor of Electrical Engineering at Yale University, where he leads the Computer Architecture and Security Laboratory (CASLAB). Prior to joining Yale, he received Ph.D. and M.A. degrees in Electrical Engineering from Princeton University, and B.S. degree with highest honors in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign. He has received the NSF CAREER award in 2017. Jakub is the author of first book focusing on processor architecture security: “Principles of Secure Processor Architecture Design”, published in 2018. Recently, he has been promoted to the IEEE Senior Member rank in 2019. Details of Jakub’s research can be found at: https://caslab.csl.yale.edu/~jakubS