Steve is the founder of Redwood EDA, a startup focused on next-generation digital circuit design and the democratization of semiconductor technologies. He is actively driving forward the Transaction-Level Verilog standard and provides the Makerchip online IDE for open-source semiconductor design.
Formerly, as an engineer with DEC, Compaq, and Intel, Steve designed components for Alpha, Itanium, and x86 server CPUs and network architectures. Steve holds a BS in electrical engineering summa cum laude from Rensselaer Polytechnic Institute and an MS in computer science from the University of Illinois.
Our course is delivered using a cloud-based environment, incorporating open-source electronic design automation (EDA) solutions, ensuring accessibility and ease of use. Participants must bring their own laptop all ten days. All work will be done within a web browser and using provided hardware.
Digital Logic Design
Students learn modern techniques in digital logic design, simulation, and debugging. They develop various digital circuits including a RISC-V CPU core.
ASIC and FPGA Development
Students take their designs from hardware description to application-specific integrated circuit (ASIC) fabrication and learn about the tools involved in that process. They use development boards for rapid prototyping using field-programmable gate arrays (FPGAs) to test their designs.
In addition to the main class time, students have the opportunity to engage in technical, in-person bring-up and validation sessions conducted on later days after receiving their fabricated silicon.
- Learn digital logic design using schematic-style design (Wokwi) and HDL coding (Makerchip/TL-Verilog).
- Create: simple circuits, a calculator, a single-cycle RISC-V CPU, a pipelined RISC-V CPU.
- Become familiar with ASIC and FPGA flows.
- Implement a custom project for Tiny Tapeout such as:
- A customized RISC-V CPU/program.
- An enhanced calculator.
- A simple circuit of their own design.
Module 1: Digital Logic Design and Tools
Introducing digital logic design including combinational logic, sequential logic, pipelined logic, and more.
Learning online digital design tools including the Wokwi and Makerchip platforms.
Exploring the journey from hardware description to silicon using the Tiny Tapeout flow.
Hands-on design using hardware prototyping with a field-programmable logic array (FPGA) based
Tiny Tapeout evaluation board.
Module 2: RISC-V CPU Design
RISC-V ISA, compilers, and CPUs.
Building a single-cycle RISC-V CPU core.
Pipelining the RISC-V CPU core for higher performance.
Evaluating performance power and area tradeoffs.
“Taping in” the CPU using Tiny Tapeout.
Module 3: Final Project
Defining an open-ended small-team final project to design a Tiny Tapeout ASIC.
Designing and debugging the project and taping in the design.
Module 4: Post Silicon Testing
Months later, after chip fabrication
Testing packaged and mounted parts on the Tiny Tapeout boards.