- Components of process design kits (PDKs).
- What are standard cells and standard cell views?Components of process design kits (PDKs)
- Types of digital synthesis.
- Timing analysis (STA, SSTA).
- Physical design (floorplanning, power planning, Clock Tree Synthesis (CTS), and timing closure)
- Chip level planning (I/O, power planning, chip testing)
- Signoff checks (DRC, LVS, …)
- GDSII.
- Preparing for chip testing, Dos and Don’ts.
Hands-on Lab
- Model a basic processor for ASIC and understand HDL coding style for ASIC vs FPGA.
- Examine all the files in the design kit/standard cell views and understand the information provided in each file type.
- Synthesize the processor and understand the different transformations occur with each design step.Examine all the files in the design kit/standard cell views and understand the information provided in each file type.
- Implement the physical design and signoff check steps and generate the GDSII of the processor.