Dates
Jan 31, 2025 – December 31, 2025
Class Days
Online, Self-paced
97 HOURS
Course Description
This intensive learning program focuses on providing a practical approach to multiple industry leading design products offered by Synopsys. It offers an insight into the market-leading digital design products for Synthesis, Place-and-Route, and Signoff. This program has a vast coverage of courses that enables you for the deployment of advanced technologies throughout the entire design cycle. Each course has a set of video lectures accompanied by extensive and detailed hands-on labs. The courses are structured in the self-paced learning mode that enables the flexibility to learn in your own pace, time and schedule within the span of 6 months.
Mode: Online, Asynchronous link provided upon approved registration
Times: Self-paced; complete within 180 days of start date
If you have any questions, please contact Dr. Eslam Tawfik
Course Instructor; This training is supported by Synopsys Self-Paced Learning
Course Prerequisite
No Prior Experience Required
Target Audience
DoW, Government, or Government Affiliated employees only. Must register with your organizational email, or currently be a member of the MEST Group on nanoHUB. You will be notified of acceptance by email.
• New hires from digital design teams
• Career starters interested in the digital design domain
• ASIC, Front-end and layout designers, and verification engineers
• Graduate students from Bachelor’s and Master’s degrees
Registration
Registration is open!
This course will cover the following topics in detail (These modules must be completed in order listed):
Library Compiler (3 Hours)
Description
In this course, you will learn details of the Library Compiler of technology library and liberty. You will learn the creation of physical library and its characterization data. Multiple detailed modules will cover library module file structure, library creation guidelines with physical library preparation as well as fusion library creation.
Prerequisites
While prior knowledge of Physical Design is not needed, knowledge of general (non-tool specific) standard cell-based library creation concepts and terms is helpful. An understanding of basic digital ASIC design concepts is assumed, including:
- Combinational and sequential logic functionality
- Setup and hold timing
- Low power
- Advance nanometer features
Design Compiler NXT: RTL Synthesis (10 Hours)
Description
In this course, you will learn the RTL synthesis flow: Using Design Compiler® NXT in Topographical mode to synthesize a block-level RTL design to generating a final gate-level netlist with acceptable postplacement timing and congestion. All topics are accompanied by engaging hands-on lab exercises.
Modules of read in hierarchical block-level RTL designs; load libraries, technology data and floorplan constraints; apply and verify constraints for complex design timing; use timing- and congestion-focused Design Compiler Ultra and Design Compiler NXT optimization features, which includes the SPG flow, to achieve postplacement timing closure and acceptable congestion.
Modules of analyze synthesis results for timing and congestion; generate output data required by physical design or layout tools. Verify the logic equivalence of synthesis transformations (such as datapath optimizations and register retiming) to that of an RTL design using Formality®.
Hands-on labs to reinforce and practice key topics discussed in the lecture. Optionally, you will verify the logic equivalence of synthesis transformations (such as data path optimizations and register retiming) to that of an RTL design using Formality.
All the commands and flows covered in the course are printed separately in a 15-page Job Aid, which you can refer to back at work.
Prerequisites
To benefit the most from the material presented in this course, you should:
- Have prior experience with Design Compiler is not needed.
- Understand basic digital ASIC design concepts, including combinational and sequential logic functionality, and setup and hold timing.
- Be able to work in a UNIX/X-windows environment, using a text editor such as emacs, vi, pine (required for labs).
Fusion Compiler: Design Creation and Synthesis (10 Hours)
Description
In this course, you will learn to use Fusion Compiler to perform complete physical synthesis, which is the unification of traditional synthesis and IC Compiler II placement functionality.
Modules include GUI usage and extensive GUI exercises; Creating the design library and referencing standard cell and IP libraries, reading RTL and dealing with “dirty” or incomplete RTL; Understanding objects, blocks and application options; Details of the seven optimization stages of the compile_fusion flow and the absolute minimum setup required for physical synthesis. How NDM cell libraries are constructed and what source data is required and the library configuration flow; Loading UPF and dealing with incomplete or non-existing UPF; Loading floorplan data and using Fusion Compiler’s advanced auto-floorplanning features; Performing MCMM setup (modes, corners, scenarios), fixing timing setup issues, and accounting for on-chip variation; Configuring concurrent clock and data (CCD) optimization, dealing with macro skew requirements and performing set up for CTS (non-default routing rules, clock cell selection). Module of power optimization which includes leakage, dynamic and total power optimization, multibit optimization, clock gate insertion, XOR self-gating; Various techniques to improve timing and congestion, DesignWare, and pre-route layer estimation technologies. Hierarchical synthesis using abstracts is described in detail.
Prerequisites
Prior working knowledge of Design Compiler Graphical is expected. Superficial knowledge of ICC II placement is helpful.
Fusion Compiler: Design Implementation (13 Hours)
Description
Enroll in this course to learn how to use Fusion Compiler to continue the unified flow after compile_fusion. 8 detailed modules will cover clock tree synthesis, routing, post-route-optimization as well as signoff operations on block-level designs. The course includes extensive hands-on labs with detailed scripts.
The course assumes that you have used Fusion Compiler to create a synthesized and placed design using compile_fusion, and that you have an understanding of the required scenario timing and power setup.
The lectures are accompanied by detailed hands-on labs, which you will run on our cloud-lab platform. No software installation is necessary.
Prerequisites
To benefit the most from the material presented in this workshop, students should:
Have taken the Fusion Compiler Synthesis workshop
OR
Possess equivalent knowledge with Fusion Compiler including:
- Load an existing design
- Use the GUI to interact with a design (analyze, query, …)
- Use corners, modes and scenarios to constrain the design
- Use concurrent clock and data optimization in Fusion Compiler
Fusion Compiler: DFT Insertion (10 Hours)
Description
In this course, you will learn about using Fusion Compiler to perform Scan Synthesis.
We start with fundamentals of Scan testing, the supported Scan synthesis flows in Fusion Compiler, running and debugging Design Rule Checks, then proceed to building scan chains at the block-level.
We will then cover fine-grained control of scan chain architecture, inserting Test Points to improve test coverage, bottom-up scan synthesis flows, On-Chip Clocking (OCC) controller insertion and core wrapper insertion.
We will then proceed to use TestMAXTM DFT to insert additional DFT hardware to reduce the test time and test data volume required for a given fault coverage.
We will conclude with exporting files to Synopsys TestMAX ATPG tool and Place & Route scan reordering.
Prerequisites
To benefit the most from the material presented in this course, you should:
- Have a basic understanding of and performing Fusion Compiler synthesis (knowledge of Fusion Compiler: Synthesis and Design Implementation Jumpstart course or equivalent)
- Familiar with UNIX
- Knowledge of concepts in TestMAX DFT course (Full class or Jump start) will be beneficial
Fusion Compiler: SoC Design Planning (13 Hours)
Description
In this hands-on course, you will use Fusion Compiler or IC Compiler II to create chip and block-level floorplans using a hierarchical (top-down) design planning approach. The focus is on multi-voltage (UPF) system-on-a-chip (SoC) designs with multiple levels of physical hierarchy, which can contain a mix of multiply-instantiated blocks (MIBs), black boxes, and partial netlists.
Prerequisites
To benefit the most from the material presented in this course, you should:
- An understanding of fundamental floorplanning concepts is required. It is assumed that the requirements to create a good floorplan are known.
- While prior working knowledge of Fusion Compiler or IC Compiler II would be very helpful, it is not required. The workshop, however, does assume a basic understanding of the design/timing setup and configuration concepts (corners/modes/scenarios).
PrimeTime Foundation (4 Hours)
Description
PrimeTime is the industry standard for STA, timing closure, and signoff.
This course provides an overview on how to perform Static Timing Analysis (STA) and Signal Integrity (SI) analysis on a block or chip-level design using the PrimeTime Suite of tools.
In this course, you will learn to:
- Identify constraints that are either incomplete or incorrect causing invalid timing violations or hiding real timing violations
- Generate reports by executing the appropriate high-level summary reports initiating your analysis, customizing, and interpreting detailed timing reports for debugging
- Exercise several timing checks on the design as well as analyze designs with complex timing requirements
- Address several signoff or timing closure topics including Path-Based Analysis (PBA), CCS Timing and Noise Libraries, Parametric On-Chip Variation (POCV), Advanced Waveform Propagation (AWP), ECO What-if analysis, Distributed Multi Scenario Analysis (DMSA)
Prerequisites
To benefit the most from the material presented in this course, you should:
- Have a basic understanding of digital IC design
- Understand elements of gate-level design:
o Chip versus block level
o Sequential versus combinational logic
o Clock tree versus data path
o Pre-layout versus post-layout differences - Have familiarity with UNIX and a UNIX text editor of your choice
StarRC Foundation (4 Hours)
Description
IEnroll in this eLearning course to learn the fundamentals of extraction and the usage of the StarRC tool for parasitic extraction in seven modules. Starting from the basics of extraction, this course covers the gate-level and transistor-level extraction flows along with important features like process modeling effects, integrated field solver, and metal fill extraction.
Prerequisites
To benefit the most from the material presented in this workshop, students should:
- Get familiar with the place and route tools and flows
- Have knowledge of the physical design verification tools
IC Validator: Physical Verification – Foundation course for Block Designers (11 Hours)
Description
This course offers an overview of launching and executing essential Physical Verification flows including DRC, LVS and Fill using Synopsys IC Validator tool. Course provides introduction to layout editor IC Validator Work Bench and the utility to merge layouts and fill using ICVWB. For faster convergence, course introduces to quick iteration process of DRC and LVS using ICV utility. Ideal for professionals seeking fundamental knowledge of IC Validator tool and its usage in PV flows.
Prerequisites
To benefit the most from the material presented in this course, you should be able to:
- Have a basic understanding of physical layout
- Have familiarity with UNIX
- No prior knowledge of IC Validator or experience is needed
IC Validator: Physical Verification – Foundation course for Chip Designers (13 Hours)
Description
This course offers an overview of launching and executing essential Physical Verification flows including DRC, LVS and Fill using Synopsys IC Validator tool. Course provides introduction to layout editor IC Validator Work Bench and the utility to merge layouts and fill using ICVWB. For faster convergence, course introduces to quick iteration process of DRC and LVS using ICV utility. Ideal for professionals seeking fundamental knowledge of IC Validator tool and its usage in PV flows.
Prerequisites
To benefit the most from the material presented in this course, you should be able to:
- Have a basic understanding of physical layout
- Have familiarity with UNIX
- No prior knowledge of IC Validator or experience is needed
Fusion Platform Reference Methodology (2 Hours)
Description
In this course, you will learn details about the Fusion Platform Methodology – overview, organization and structure with a lab example. You will learn how Fusion Platform Methodology is a directly deployable RTL2GDSII flow solution. It is built upon Synopsys Fusion Compiler and analysis product Reference Methodologies. It scales the benefits of improved out of the box QOR and user experience across a multi-user, multi-block project platform.
Prerequisites
To benefit the most from the material presented in this course, you should:
- Have prior knowledge of Fusion Compiler or IC Compiler II
- Have taken the Fusion Compiler or IC Compiler II: Block-level Implementation OR
- Possess equivalent knowledge with Fusion Compiler or IC Compiler II including:
- Load an existing design, knowledge of general (non-tool specific) standard cell-based placement, CTS, and routing concepts and terms is helpful