Recommended Learning Journey for a Digital Designer

Registration

Registration is open!

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Registrations are being accepted during the final preparations for the course. We anticipate the course to be available on January 31, 2025 and open through March 31, 2025.

Design Compiler NXT: RTL Synthesis (10 Hours)

Description

In this course you will learn the RTL synthesis flow: Using Design Compiler® NXT in Topographical mode to synthesize a block-level RTL design to generating a final gate-level netlist with acceptable postplacement timing and congestion. All topics are accompanied by engaging hands-on lab exercises.  

Modules of read in hierarchical block-level RTL designs; load libraries, technology data and floorplan constraints; apply and verify constraints for complex design timing; use timing- and congestion-focused Design Compiler Ultra and Design Compiler NXT optimization features, which includes the SPG flow, to achieve postplacement timing closure and acceptable congestion. 

Modules of analyze synthesis results for timing and congestion; generate output data required by physical design or layout tools. Verify the logic equivalence of synthesis transformations (such as datapath optimizations and register retiming) to that of an RTL design using Formality®. 

Hands-on labs to reinforce and practice key topics discussed in the lecture. Optionally, you will verify the logic equivalence of synthesis transformations (such as data path optimizations and register retiming) to that of an RTL design using Formality. 

All the commands and flows covered in the course are printed separately in a 15-page Job Aid, which you can refer to back at work.

Prerequisites

To benefit the most from the material presented in this course, you should:

• Prior experience with Design Compiler is not needed. 
• Understand basic digital ASIC design concepts, including combinational and sequential logic functionality, and setup and hold timing. 
• Be able to work in a UNIX/X-windows environment, using a text editor such as emacs, vi, pine (required for labs). 

Fusion Compiler: Design Creation and Synthesis (10 Hours)

Description

In this course, you will learn to use Fusion Compiler to perform complete physical synthesis, which is the unification of traditional synthesis and IC Compiler II placement functionality.

Modules include GUI usage and extensive GUI exercises; Creating the design library and referencing standard cell and IP libraries, reading RTL and dealing with “dirty” or incomplete RTL; Understanding objects, blocks and application options; Details of the seven optimization stages of the compile_fusion flow and the absolute minimum setup required for physical synthesis. How NDM cell libraries are constructed and what source data is required and the library configuration flow; Loading UPF and dealing with incomplete or non-existing UPF; Loading floorplan data and using Fusion Compiler’s advanced auto-floorplanning features; Performing MCMM setup (modes, corners, scenarios), fixing timing setup issues, and accounting for on-chip variation; Configuring concurrent clock and data (CCD) optimization, dealing with macro skew requirements and performing set up for CTS (non-default routing rules, clock cell selection). Module of power optimization which includes leakage, dynamic and total power optimization, multibit optimization, clock gate insertion, XOR self-gating; Various techniques to improve timing and congestion, DesignWare, and pre-route layer estimation technologies. Hierarchical synthesis using abstracts is described in detail.

Prerequisites

Prior working knowledge of Design Compiler NXT is expected. Superficial knowledge of ICC II placement is helpful.

Fusion Compiler: DFT Insertion (10 Hours)

Description

In this course you will learn about using Fusion Compiler to perform Scan Synthesis.  

We start with fundamentals of Scan testing, the supported Scan synthesis flows in Fusion Compiler, running and debugging Design Rule Checks, then proceed to building scan chains at the block-level.  

We will then cover fine-grained control of scan chain architecture, inserting Test Points to improve test coverage, bottom-up scan synthesis flows, On-Chip Clocking (OCC) controller insertion and core wrapper insertion. 

We will then proceed to use TestMAX DFT to insert additional DFT hardware to reduce the test time and test data volume required for a given fault coverage. 

We will conclude with exporting files to Synopsys TestMAX ATPG tool and Place & Route scan reordering.

Prerequisites

To benefit the most from the material presented in this course, you should:

• Have a basic understanding of Fusion Compiler synthesis (knowledge of Fusion Compiler: Synthesis and Design Implementation Jumpstart course or equivalent)
• Familiar with UNIX
• Knowledge of concepts in TestMAX DFT course (Full class or Jump start) will be beneficial

Fusion Compiler: SoC Design Planning (13 Hours)

Description

In this course you will use Fusion Compiler or IC Compiler II to create chip and block-level floorplans using a hierarchical (top-down) design planning approach. The focus is on multi-voltage (UPF) system-on-a-chip (SoC) designs with multiple levels of physical hierarchy, which can contain a mix of multiply-instantiated blocks (MIBs), black boxes, and partial netlists.

Initial modules give you a quick overview of the DP flow, and then goes into the details of creating your initial flip-chip layout, and performing design exploration to decide on the chip’s multi-level physical partitions. You then learn how to split chip level constraints and UPF. You will create block abstracts of the design and move on to automatic shaping of the blocks and voltage areas within the chip, as well as hierarchical macro and standard cell placement. This is in tandem with congestion and connectivity analysis.

It covers Pattern-based Power Network Synthesis (PPNS) to design a complex multi-voltage chip-level power network, which is then built for each sub block in an automated and distributed fashion. Power switch insertion is also discussed. Next, the discussion moves to pin placement, including topological constraints and a detailed discussion on feedthroughs.

It also covers covers hierarchical timing estimation and timing budgets, which are used for block implementation. Top-level integration and implementation as well as budget shells are then also discussed and how they are used for top-level implementation. The day wraps up by explaining how to use black boxes throughout the design planning flow.

Prerequisites

To benefit the most from the material presented in this course, you should:

• Have a basic understanding of fundamental floorplanning concepts is required. It is assumed that the requirements to create a good floorplan are known.
• Prior working knowledge of Fusion Compiler or IC Compiler II would be very helpful, it is not required.
• The workshop, however, does assume a basic understanding of the design/timing setup and configuration concepts (corners/modes/scenarios).

StarRC Foundation (4 Hours)

Description

In this course you will learn the fundamentals of extraction and the usage of the StarRC tool for parasitic extraction in seven modules. Starting from the basics of extraction, this course covers the gate-level and transistor-level extraction flows along with important features like process modeling effects, integrated field solver, and metal fill extraction.

Prerequisites

To benefit the most from the material presented in this course, you should:

• Have familiarity with the place and route tools and flows
• Have knowledge of the physical design verification tools

IC Validator User (6 Hours)

Description

In this course you will learn to use IC Validator to perform physical verification tasks such as Design Rule Checking (DRC) and Layout vs Schematic (LVS) verification.  In the DRC section, the user will go through a basic DRC flow and execute complete DRC runsets and verify the results. Exploring how to get maximum throughput with IC Validator is also covered.  In the LVS section, the user will go through a basic LVS flow and review the different kinds of errors reported during LVS.  The user will use ICV VUE to debug errors and use VUE Short Finder to debug shorts in the design.

Prerequisites

To benefit the most from the material presented in this course, you should:

• Possess an awareness of basic physical verification concepts
• Have basic working knowledge of any layout editor
• Be able to use a text editor (vi, vim, emacs) in a UNIX environment

Fusion Platform Reference Methodology (2 Hours)

Description

In this course, you will learn details about the Fusion Platform Methodology – overview, organization and structure with a lab example. You will learn how Fusion Platform Methodology is a directly deployable RTL2GDSII flow solution. It is built upon Synopsys Fusion Compiler and analysis product Reference Methodologies. It scales the benefits of improved out of the box QOR and user experience across a multi-user, multi-block project platform.

Prerequisites

To benefit the most from the material presented in this course, you should:

• Have prior knowledge of Fusion Compiler or IC Compiler II
• Have taken the Fusion Compiler or IC Compiler II: Block-level Implementation OR
• Possess equivalent knowledge with Fusion Compiler or IC Compiler II including:
• Load an existing design, knowledge of general (non-tool specific) standard cell-based placement, CTS, and routing concepts and terms is helpful