Course Details
Aug 17, 2026 – Sep 14, 2026
(No class on September 7
due to Labor Day)
4 WEEKS | 12 HOURS
12:00 PM – 1:30 PM ET
Mondays and Thursdays
Course Description
Preliminary topics to cover (Can be subject to change)
Advanced Packaging Technologies
Details physical unit process integration, multi-die substrate fabrication, and global advanced packaging supply chains. The material covers advanced substrate process flows, foundry/OSAT platform architectures, and reliability and performance optimization. The curriculum highlights next-generation manufacturing paradigms: sub-micron copper-to-copper (Cu-Cu) hybrid bonding, large-body 2.5D and 3D advanced substrates and fan-out
wafer level packaging (FOWLP), co-packaged optics (CPO), glass core substrates, and panel-level packaging (PLP).
Session 1: Advanced Packaging Ecosystem Overview
Covers the structure of the industry, including the major designers, IDMs, foundries, OSATs, and substrate suppliers. Reviews the materials and equipment supply chain along with emerging manufacturing trends. Course participants will gain an understanding of the industry landscape as well as a mapping of which companies produce which packaging technology for which product sets.
Session 2: General Architectures, Components, and Process Flows
Provides descriptions of the components, materials, and general process flows from die prep to reconstituted wafer or substrate manufacturing to assembly, as well as an overview of the many variations of advanced packaging architectures and related process steps. Covers chip-scale package and wafer-level packaging, fan-out vs fan-in, bonding technologies, and advanced substrates and interposers.
Session 3: High-Density Organic Substrates
Participants will gain a more thorough understanding of the architecture and process flow for advanced organic substrates. The session will begin with a detailed look at the process flow at each layer from through-core via, build-up, RDL and surface insulator, bonding layer, and assembly. It will then review trade-offs in materials selection and process selection (eg. laser drill vs photo-imageable dielectric, semi-additive process vs damascene, microball vs ubump vs Cu pad)
Session 4: Interposers, Embedded Interconnect, and Fan-out Wafer Level Packaging
Reviews innovations that have enabled interconnect density scaling, including silicon, glass, and organic RDL interposers, System-in-Package 2.5D heterogeneous integration architectures enabling disaggregation and scale-out; techniques and architectures for integrating embedded components, including passive devices and high density interconnect chips. The class will also compare fan-out wafer level packaging with advanced substrates for achieving the integration of these interconnect density solutions.
Session 5: Deep Dive on State of the Art Packaging Platforms
Participants will gain a detailed understanding of the leading edge 2.5D and 3D advanced packaging platforms from the major foundries/IDMs/OSATs. The class will dive into their architectures for heterogeneous integration and the technologies that are improving performance for AI accelerators, data centers, and high performance compute.
Session 6: Addressing Challenges in Reliability, Performance Scaling, and Affordability
Reviews some of the major challenges in advanced packaging along with the design and material selection trade-offs involved in resolving them. It will include warpage, delamination, moisture, and cracking mitigation, CTE mismatch, RDL pitch scaling, RC considerations, and energy/bit optimization. Participants will also gain an understanding of total package cost considerations.
Session 7: Emerging Tech: Hybrid Bonding, Through-“x” Vias
This session explores next-generation vertical interconnect technologies that enable ultra-high bandwidth for advanced heterogeneous integration. Participants will learn the principles, process flows, and challenges of hybrid bonding, including Cu-Cu direct bonding, oxide bonding, alignment accuracy, CMP requirements, and common defects and techniques for mitigating them. It will also review the through-substrate via (TSV, TGV, etc) process, reliability challenges, and trends.
Session 8: Emerging Tech: Co-packaged Optics, Wafer-scale packaging, Glass Core & Next-gen Materials
This session introduces co-packaged optics (CPO) and wafer-scale packaging as solutions for meeting the bandwidth and scale requirements for next-generation AI and data center systems. Participants will learn how photonics and electronics are integrated to overcome electrical signal and power limitations. The session also covers wafer-scale integration challenges including thermal management, mechanical reliability, signal integrity, and large-area assembly. Lastly, it will examine trends toward panel-scale manufacturing and highlight next-gen materials such as glass core and ultra-low loss dielectrics.
Course Prerequisites
No prior experience in advanced IC packaging or assembly is required.
Target Audience
This course is designed for electrical engineers, materials scientists, mechanical engineers, and manufacturing professionals involved in the design, fabrication, and testing of integrated circuits (ICs). It is also highly relevant for technical managers and supply chain professionals in the semiconductor industry.
Registration
Registration is open!
Tom McCune
Course Instructor
Tom McCune specializes in advanced packaging, with experience in substrate/interposer process development and integration, materials R&D, 2.5D and 3D heterogeneous integration, glass panel substrates, and equipment design and sourcing. Tom has built a career at the intersection of emerging technologies, materials science, pilot line integration, and strategic program development—bridging the gap between cutting-edge research and scalable manufacturing.
At Natcast he supported key initiatives under the CHIPS and Science Act. He identified advanced packaging research opportunities to improve AI, HPC, and data center efficiency. In parallel, Tom conducted technical evaluations of U.S.-based startups for the Natcast Investment Fund. His advisory work on hybrid bonding assembly and process flow design informed early planning and infrastructure for the NAPPF, ensuring alignment between R&D capabilities and commercial manufacturing readiness. Tom also developed review packages to define the state of the art and future trends for FOWLP, 3D heterogeneous integration, hybrid bonding, & emerging substrate architectures.
Prior to Natcast, Tom was a Senior Advanced Packaging R&D Engineer at Intel, driving pathfinding and integration for EMIB and Foveros technologies. He led the development and qualification of next-generation solder resist materials for scaling interconnect pitch, improving lithography capability, yield, and reliability for early test vehicles. As the solder resist technical lead, he coordinated model-based problem-solving efforts with cross-functional teams in design, assembly, and integration. Within Intel’s glass substrates program, Tom led manufacturing readiness, process design, and supplier collaboration for new substrate tooling, leading to Intel’s first demonstration of Foveros 3D Meteor Lake substrates with glass panel cores.
Tom holds an M.S. & B.S. in Materials Science & Engineering from Cornell University. He now brings his research and industry experience to startups, research institutions, and industry partners seeking to define and deploy the next generation of advanced packaging technologies.
Areas of Expertise: Advanced Packaging- 2.5D and 3D heterogeneous integration, RDL pitch scaling, glass panel substrates, hybrid bonding, materials development.