• Skip to main content
  • Skip to header right navigation
  • Skip to site footer
MEST Center

MEST Center

National Microelectronic Security Training Center

  • Home
  • About Us
    • Advisory Board
    • Contributors
    • Directory
  • Trainings
    • Join us on nanoHUB!
    • Webinars
    • Micro Certificates
    • Macro Certificates
    • Modules
  • Schedule
  • Contact Us
  • Partners
    • nanoHUB
    • SCALE

Introduction to Integrated Circuit Packaging and Assembly

Dates

August 24, 2026 – September 21, 2026

4 Weeks


Class Days

Mondays

August 24, 2026
August 31, 2026
September 14 2026
September 21, 2026


Meeting Times

4:00 PM – 5:30 PM

6 Hours

Course Description

This 6-hour course introduces the structures, materials, and processes used to package integrated circuits. Participants will learn how wafers and die become finished components through dicing, die attach, wire bonding, flip-chip bonding, solder bumping, underfill, encapsulation, lid attach, and package marking. The course also introduces common package types, including plastic encapsulated, ceramic/hermetic, BGA, chip-scale, and metal-lidded flip-chip packages.

Course Details

The course is designed for a broad technical audience, including students, researchers, engineers, government personnel, defense contractors, failure analysts, materials analysts, counterfeit detection specialists, and professionals working with microelectronic components or systems. General familiarity with electronics, microelectronics, materials, or hardware systems is helpful, but no prior IC packaging experience is required. Topics include IC package functions, common package types, wafer-to-package assembly, wire bonding, flip-chip assembly, BGAs, lead frames, substrates, solder balls, underfill, encapsulants, lids, package markings, materials selection, reliability considerations, and emerging 2.5D/3D packaging approaches.

Learning outcomes

Participants will be able to identify major IC package types, describe how packaged components are assembled, recognize key package layers and materials, compare wire-bonded, flip-chip, BGA, ceramic, plastic, and metal-lidded package structures, explain how packaging materials affect performance and reliability, and understand common package marking approaches used for traceability, inspection, and component identification.


Course Prerequisites


No Prior Hardware Experience Required

Target Audience


Designed for U.S. citizens working in the Department of War, Government, or Government-affiliated employees, industry, as well as college students and faculty. Must register with your organizational email, and will be notified of acceptance within one week of the course start date.

Registration

Registration is open!


REGISTER

Shane Smith

Course Instructor

Dr. Shane Smith (Ph.D., Electrical and Computer Engineering, The Ohio State University) is a Research Scientist at The Ohio State University Electroscience Lab and President and co-founder of SenseICs Corporation. Shane has worked for more than 25 years designing, producing, and maintaining electronic systems used in integrated circuit research, high-energy physics experiments at CERN and the Stanford Linear Accelerator Center, and other applications. His broad expertise covers a range of electrical engineering activities, including the design and development of radiation-hard mixed-signal ASICs, FPGA-based data acquisition systems, medical imaging electronics, chemical vapor deposition diamond detectors, and high-voltage power supply systems. Additionally, his academic publications, which include more than 80 peer-reviewed conference papers and journal articles, have been cited more than 20,000 times.


  • LinkedIn
  • Email MEST Center
  • Join us on nanoHUB!