Modeling and Verification of Analog and Mixed Signal ICs from Concept to Post Layout Simulation

Course Description

This course provides a practical overview of modeling and verification methods for analog and mixed signal integrated circuits. The course begins with early stage design planning, where behavioral models, real number models, and other simplified descriptions can be used to explore system functionality before full transistor level design is available. These models are useful for evaluating architecture choices, checking signal flow, developing control concepts, and identifying potential design risks early in the process.

The course then moves into schematic level simulation using SPICE based methods. Topics include operating point analysis, DC sweeps, AC analysis, transient simulation, noise analysis, and other common simulation approaches used to verify circuit functionality. The course also introduces PVT analysis, Monte Carlo analysis, and sensitivity analysis as tools for evaluating circuit robustness, variation tolerance, and expected parametric yield.

A major focus of the course is the interaction between analog and digital domains in mixed signal systems. The course will discuss mixed signal simulation approaches that combine transistor level analog blocks with digital logic, behavioral models, or HDL based control blocks. This includes practical discussion of how to verify feedback loops, control logic, digital to analog interfaces, and analog to digital interactions within larger integrated systems.

The course also covers the transition from schematic design to layout aware verification. Topics include layout implementation concerns, parasitic extraction, post layout simulation, and comparison of pre layout and post layout results. Particular emphasis will be placed on recognizing when parasitic resistance and capacitance can degrade circuit performance, how to debug layout induced changes, and how to decide whether a design is ready for tapeout.

The final portion of the course introduces hierarchical verification and formal verification concepts in the context of analog and mixed signal IC design. Rather than treating verification as a single final step, the course presents a layered approach where individual blocks, interfaces, control loops, and top level system behavior are checked progressively throughout the design process.

The course will include lab exercises associated with the main technical modules. These lab exercises will use a real world PDK from an advanced nanometer technology node so that attendees can work with practical modeling, simulation, and verification considerations that are representative of modern IC design flows. The first module will provide background and establish the overall analog and mixed signal design flow. The remaining modules will include guided lab components that allow attendees to apply the concepts through simplified modeling, simulation, analysis, and verification exercises.

Suggested course modules and lab components

1. Analog and mixed signal IC design flow from concept to tapeout
   This module provides background on the overall design and verification flow. It introduces how modeling, simulation, layout, extraction, and verification fit together across the IC development process.
2. Early concept development using behavioral and real number models
   Lab component: Attendees will develop or evaluate a simplified behavioral model that represents the expected function of an analog or mixed signal block at a high level of abstraction.
3. VerilogA and simplified modeling approaches for analog and mixed signal systems
   Lab component: Attendees will work with a simplified VerilogA style model or equivalent behavioral description to understand how analog behavior can be represented before full transistor level implementation.
4. Circuit level SPICE simulation of analog building blocks
   Lab component: Attendees will run or review schematic level simulations such as operating point, DC sweep, AC analysis, transient response, and noise analysis for a representative analog circuit block.
5. Mixed signal simulation of analog blocks, digital control logic, and feedback loops
   Lab component: Attendees will examine a mixed signal simulation example that combines analog behavior with digital control logic or interface signals, with emphasis on signal interaction and system level functionality.
6. PVT, Monte Carlo, and sensitivity analysis for robustness and yield
   Lab component: Attendees will evaluate simulation results across process, voltage, and temperature corners and use Monte Carlo or sensitivity analysis to identify key design limitations and variation sensitive parameters.
7. Layout aware verification using parasitic extraction and post layout simulation
   Lab component: Attendees will compare pre layout and post layout simulation results to identify the impact of parasitic resistance and capacitance on circuit performance.
8. Hierarchical verification from block level simulations to full system validation
   Lab component: Attendees will develop a hierarchical verification checklist that connects block level simulations, interface checks, and top level system validation.
9. Formal verification concepts for digital control logic, interfaces, and golden model comparison Lab component: Attendees will review a simplified golden model or expected behavior specification and compare it against an implemented control sequence, state machine, or mixed signal interface behavior.